November 2008Recent Lattice webcasts are available on demand from the Lattice website and are shown in the table below. These one-hour webcasts are presented by Lattice technical staff and may include software demonstrations and question and answer sessions. To view any of the webcasts, go to the webcasts section of the Lattice website and select your topics of interest.
| Webcast Title | Featured Product | Original Webcast Date | Abstract |
|---|---|---|---|
| Instant-On, Non-Volatile FPGAs for Automotive Systems | LA-LatticeXP2 FPGA Family | 9/17/08 | While SRAM-based FPGAs have been used in automotive applications for several years, designers dislike the requirements of an external boot device and slow startup times. Lattice provides a solution to this problem with the recent introduction of the non-volatile, instant-on, AEC-Q100 qualified LatticeXP2 FPGA. Attend this webcast for detailed information on the LatticeXP2 FPGA and how it benefits automotive electronic designs. |
| FPGA Power Calculation Techniques | ispLEVER Design Software | -- | This webcast provides an introduction to how power estimation is accomplished by FPGA design tools, as well as which device features consume power and when. Lattice FPGAs and design tools will be used to illustrate several power calculation scenarios. This demonstration will help you to adopt a power verification strategy along with traditional simulation and static timing analysis. |
| Quick Timing Closure - Simulation & Debug of FPGA Designs | ispLEVER Design Software and Lattice FPGAs |
9/15/08 |
Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help achieve timing closure faster. Don’t make the same mistake, identify and address problems earlier using a simulator and STA tools in concert. This webcast uses a Lattice reference design to show you how to use STA results to prepare a test bench, extract timing models from FPGA design tools, understand simulation results, and identify/trace problems before you program your Lattice FPGA. To wrap-up the verification process, designers can compare timing results against functional results to ensure design integrity. |
© Lattice Semiconductor Corporation 2012
