November 2007

New LatticeMico32 Demo with DDR Memory and VGA Monitor

This demo brings together the LatticeMico32 soft processor with DDR2 memory controller IP and VGA monitor IP on the LatticeECP-based LatticeMico32/DSP Development Board. The demo focuses on the board’s VGA interface, with a DDR SDRAM module used both for executing code and serving as video memory. The LatticeMico32 processor, a WISHBONE master, writes to the video memory. A VGA controller, also a WISHBONE master, reads from the video memory. 

The demo is available from the LatticeMico32 web page on the Lattice website. The LatticeMico32 DDR SDRAM Demonstration User's Guide provides system requirements and complete details.

Features

The following features are demonstrated with this setup.

• Co-location of the FPGA bitstream and the software application in the SPI configuration Flash.
• Processor wake-up and execution of boot code from the SPI Flash.
• Processor executes code from a copy stored to the external DDR SDRAM.
• The DDR SDRAM is partitioned into video and software code sections.
• Processor updates the contents of the video memory while the VGA master interface reads the video memory contents.

Setup

The demonstration is simple to set up and run. Included in the zipped demo package is documentation that provides step-by-step instructions for generating the prepackaged outputs, since that is one of the goals of this demonstration. Also provided in the package are all the necessary files, including the final bitstream, the application executable, and an Intel Hex file that contains the merged bitstream and the bootable application executable. The projects used for creating these outputs are also provided as part of the zipped package. What could be easier?

The demo requires a user-supplied DDR SDRAM on a SODIMM module. The documentation provides the details of the module used in the development of the demo.

What You Will Learn from this Demo

There is much you will learn from this demo, such as seeing the WISHBONE bus in operation. But some key things to understand include the following:

• How to prepare the LatticeMico32 software application for SPI Flash deployment.
• How to generate a SPI Flash image containing the FPGA bitstream and the LatticeMico32 software application that can be programmed into the SPI Flash using ispVM System software.
• How to incorporate custom components into the LatticeMico32 platform framework. This exercise incorporates the VGA controller written in VHDL into the Verilog-based LatticeMico32 platform framework as a custom component

Results 

The microprocessor executes simple graphic functions and displays them on the VGA monitor. Below is a screen snapshot of the results.

It does not take complicated graphics to demonstrate the shared memory or the WISHBONE bus in operation.  Take the application source and modify and/or add graphic functions for yourself. That’s what the demo is all about.