November 2007
Which types of on-chip debug and analysis tools does Lattice support?
The new Reveal software, included in ispLEVER 7.0 SP1, supports FPGA on-chip debug for the following FPGA families:
The Reveal Logic Analyzer, which replaces the ispTRACY Logic Analyzer, allows you to configure trigger settings and extract information from a programmed device through JTAG ports. It interfaces directly to the Reveal cores in the design. You can set up triggers, select capture modes, and run or stop the triggers. The Reveal Logic Analyzer displays the data captured on the silicon according to the settings that you specify. It consists of the Reveal Inserter and the Reveal Analyzer.
The Reveal Inserter enables you to select which design signals to use for debug tracing or triggering, then generates debug logic on the basis of these signals and their usage. After generating the required logic, it generates a modified design with the necessary debug connections and links it to the signals.
The Reveal Logic Analyzer helps you debug your FPGA circuitry by allowing the dynamic setting of all trigger conditions and the ability to view captured data in a waveform view or export the data as VCD or an ASCII file.
Reveal Design Flow
© Lattice Semiconductor Corporation 2012
