May 2010

Low-Cost Serial RapidIO Solutions for Baseband Processing Applications

The Serial RapidIO (SRIO) interconnect architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). It enables chip-to-chip, board-to-board, and system-to-system communication and is targeted at the wireless infrastructure, backplanes, embedded/industrial control, storage and military/aerospace markets.

First Low-Cost, Low-Power FPGA with Serial RapidIO 2.1 Support

Lattice licensed the Serial RapidIO 2.1 Endpoint IP core from Praesum Communications and has full rights to use, modify and sub-license the core. This IP core supports 1x, 2x and 4x lane configurations as well as serial data rates of 1.25, 2.5, 3.125 GBaud. It implements physical layer, transport layer, maintenance transaction handling and error management extensions. The solution includes a logical layer reference design as well.

The combination of the Serial RapidIO 2.1 IP core and the award-winning LatticeECP3 FPGA enables designers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost.

SRIO in Baseband Processing Applications

Today, Serial RapidIO is the key data-plane interconnect in 3G and 4G base stations. The figure below shows a typical baseband card that utilizes microprocessors, ASICs, FPGAs and multiple DSPs on a single board. A base station architecture may use one or more of these baseband cards.

Baseband Card Architecture

From the figure above it is clear that there are three key steps in the data flow through the system. Using the low-cost, low-power LatticeECP3 FPGA along with various IP cores such as SRIO 2.1, CPRI, and SGMII and Gb Ethernet PCS can help system designers reduce system cost and power.

1. First, the baseband data coming from the antenna (RRH) must be bridged from CPRI to SRIO to allow interfacing to the DSPs for further processing.
   
   
   

   
   
    

2. Baseband processing is a very DSP-intensive application requiring fast number crunching and data processing. The FPGA can serve as a direct offload processor to the DSP to perform these functions. This can be done by connecting directly to the DSP or through an SRIO switch.
   
   
   

   
   
    

3. Third, the baseband data must be sent from the basestation to the network via a backhaul network. Due to the increased bandwidth requirements of 3.5/4G systems, this backhaul functionality is moving to Ethernet which requires a bridge from SRIO to a GbE/SGMII interface.
   
   
   

   
   
    

4. Other bridging applications include:

• Processor-to-processor bridge such as SRIO to PCI
• Control plane bridge for embedded processing applications such as SRIO to PCI Express
• Bridge for legacy processor or DSP interfaces

The LatticeECP3 FPGA family and the Lattice portfolio of IP cores (Serial RapidIO 2.1, CPRI, GbE/SGMII, PCI Express and various other DSP IP) help provide a comprehensive solution to meet the processing and bridging challenges often seen in baseband processing applications.

To Learn More

For additional information about the Serial RapidIO IP core or wireless solutions from Lattice, please visit the Lattice web site.