May 2010

LatticeECP3 SPI4 IP Core Released

The System Packet Interface (SPI) family of Interoperability Agreements from the Optical Internetworking Forum specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking and Ethernet applications.

Typical applications include:

• Interface between a framer (for optical networks) or a MAC (for IP networks) and a network processor
• Interface between a packet processor ASIC and a traffic manager device

SPI4 is designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10-Gigabit Ethernet based systems. The SPI4 IP core from Lattice supports up to 256 data channels with aggregate throughputs of between 3 and 12.8 Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs.

SPI4 IP Core Block Diagram

At the top level, the core is broken into two sub-blocks referred to as the SPI4 Transmitter (S4TX) and SPI4 Receiver (S4RX). The S4RX and S4TX blocks provide both status and data path functionality for the direction they serve. They provide a direct interface to the primary I/O of the device on one side (SPI4) and a device-internal FIFO interface to user logic on the other.

Also included is a user-side SPI4 “loop-around module” and a SPI4 test bench for optional use. The loop-around module loops received SPI4 data back to the SPI4 transmitter and transmits the status back to the SPI4 receiver. An FPGA top-level RTL template design is provided that includes the IP core and loop-around module which can be used without modification for simulation verification and can also be synthesized, placed, and routed “as is” for initial debugging on physical hardware. With this capability, the user can connect their system to a Lattice FPGA via a SPI4 interconnect and easily verify the speed and functionality of the core.

Software Support

The SPI4 IP core can be generated using the Lattice IPexpress tool. It is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. The GUI-based tool allows designers to specify various parameters to generate the IP core.

To Learn More

For further information on the SPI4 IP core or wireline solutions from Lattice, visit the Lattice web site or contact your local Lattice sales representative.