May 2010
LatticeECP3-35 Extends Low Power, Low Cost Benefits to Video, Security/Surveillance and Communications ApplicationsThe LatticeECP3-35 device in the award-winning, high-value, low-power LatticeECP3 mid-range FPGA family, has been fully qualified and released to volume production. This low-power FPGA is ideal for high-volume, low-power and low-cost designs in video, security/surveillance, industrial, embedded and communications applications.

A range of Intellectual Property (IP) cores, including FIR Filters, FFT, Reed-Solomon Encoders, Reed-Solomon Decoders, CORDIC, CIC, NCO for DSP functions, CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, Tri-Rate SDI PHY for serial connectivity, and DDR, DDR2, and DDR3 for memory interfaces, are available from Lattice and its partners to enable designers to develop rapid time-to-market design solutions.
The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 8.0 Service Pack 1 which provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route, on-chip logic analysis and more.
To learn more about the LatticeECP3 FPGA family, visit the Lattice web site or contact your local Lattice sales representative.