May 2010

High-Performance ADC to FPGA Interface Reference Design

Analog-to-Digital Converters (ADCs) are used to convert analog signals into digital representations that can be communicated and processed using digital logic. As demand for data has increased, higher bandwidth ADCs have become necessary to meet the system performance requirements. High-performance ADCs can be found in many applications, including:

• Wireless base station receivers
• Power amplifier linearization
• Multi-carrier, multi-mode receivers
• High interface sampling receivers
• Radar systems
• Test and measurement equipment
• Medical equipment

Easing System Transition to New High-Performance ADCs with Low-Cost FPGAs from Lattice

Systems migrating to higher sample rate/resolution ADCs often require an FPGA with high interface speed to bridge between existing hardware and the newer interface provided by the higher speed ADC. This allows designers to focus their effort on processing the ADC data within the FPGA and routing it to other parts of their system without having to worry about the timing details of high-speed ADC interfaces. Previously, only more expensive, high-end FPGAs could satisfy this requirement. The LatticeECP3 and LatticeECP2/M FPGA families provide this bridging function at lower cost and at significantly lower power.

Interface with Texas Instruments ADS64XX family of ADCs - Reference Design (RD1089)

The Analog-to-Digital Converter Interface Reference Design provides an example of how the LatticeECP3 FPGA can be used to interface to a high-speed ADC device. In this reference design, designers can see how a high-performance ADC like the Texas Instruments (TI) ADS64XX family of ADCs can interface with the LatticeECP3 FPGA high-speed LVDS I/O to reduce the number of interface signals required. This reference design receives data samples input via either one or two high-speed LVDS signals and converts the serial data to parallel word format.

ADC Interface (RD1089) Block Diagram

Serial data from the ADC converter are input via either one or two data signals, DA0 or DA1, together with a bit clock and a frame clock. The received serial data from the ADC is deserialized and provided as parallel data via the output bus DA_word. Output signal word_cap when set to ‘1’ indicates that DA_word contains valid output data.

Evaluation Platform - LatticeECP3 I/O Protocol Board and ADC-DAC Interface Card

The LatticeECP3 I/O Protocol Board and the LatticeECP3 IOP to TI ADC/DAC Adapter Board provide a convenient platform to evaluate, test and debug user designs and IP cores targeted for the LatticeECP3 FPGA on the LatticeECP3 I/O Protocol Board, that are designed to interface directly with the TI ADS6425 and DAC5682Z EVM boards. Other TI EVM boards may also be compatible with the LatticeECP3 IOP to TI ADC/DAC Adapter Board. When connected, the Lattice and TI evaluation boards lay out flat on the desktop in a mechanically stable test configuration.

LatticeECP3 I/O Protocol Board Connected to TI ADC and DAC EVMs

To Learn More

The Analog-to-Digital Converter Interface Reference Design, LatticeECP3 I/O Protocol Board User's Guide and LatticeECP3 IOP to Texas Instruments ADC/DAC Adapter Board User's Guide can be downloaded from the Lattice web site.