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LatticeNEWS May 2009

Contents

Free On-Demand Videos and Webcasts

Recent Lattice videos and webcasts are available on demand from the Lattice website and are shown in the table below. These videos and webcasts are presented by Lattice technical staff.

On-Demand Videos Available on the Lattice Website
Video Title Featured Product Abstract
LatticeECP3 Low Power Video LatticeECP3 FPGA Family The new LatticeECP3 is the lowest-power FPGA with SERDES in the industry. Watch this 5-minute video to view actual power measurements for the LatticeECP3 in the lab at multiple temperatures and compare lab measurements to ispLEVER Power Calculator power consumption estimates.
MachXO Mini Development Kit Video MachXO PLD Family and the MachXO Mini Development Kit See how easy it is to design with MachXO PLDs using the MachXO Mini Development Kit. Learn to test I2C, SPI, UART, SRAM interfaces and the 8-bit LatticeMico8 microcontroller within minutes. Then build your own design using the free downloadable source code and implement these features in less than an hour.
7:1 LVDS Interface Video LatticeXP2 and LatticeECP2/M FPGA Families While SRAM-based FPGAs have been used in automotive applications for several years, designers dislike the requirements of an external boot device and slow startup times. Lattice provides a solution to this problem with the recent introduction of the non-volatile, instant-on, AEC-Q100 qualified LatticeXP2 FPGA. Attend this webcast for detailed information on the LatticeXP2 FPGA and how it benefits automotive electronic designs.
Low-Cost PCI Express Development Kit Video LatticeECP2M FPGA Family and the PCI Express Development Kit Discover how easy it is to implement PCI Express designs using LatticeECP2M FPGAs. View this video to see the low-cost PCI Express Development Kit in action. Learn how to get to working hardware in less than 30 minutes and see two PCI Express demos: LED Segment and Scatter-Gather DMA.
On-Demand Webcasts Available on the Lattice Website
Webcast Title Featured Product  Original Webcast Date Abstract
Platform Management Using Low-Cost PLDs MachXO PLD Family
 --  PLDs are commonly used in platform management applications for housekeeping and power-up management. In this webcast, we discuss the requirements of PLDs in this scenario and look at some of the advantages of the MachXO. We will also examine some of the convenient tools that Lattice provides for quick evaluation and experimentation of the MachXO in a System-on-Chip role. Finally, we'll look at the MachXO TransFR feature and how it facilitates robust, remote updates.
ispLEVER 7.2 FPGA Design Tool Technical Rollout ispLEVER Design Software -- The ispLEVER/Pro 7.2 digital design tools suite supports supports the latest Lattice digital programmable logic devices, including the LatticeXP2 and LatticeECP2M FPGA device families, and provides all the features required to develop a design from concept to programmed device. View this presentation for an introduction to the new features in the latest version of Lattice's FPGA design tool platform, ispLEVER.
Instant-On, Non-Volatile FPGAs for Automotive Systems LA-LatticeXP2 FPGA Family 9/17/08 While SRAM-based FPGAs have been used in automotive applications for several years, designers dislike the requirements of an external boot device and slow startup times. Lattice provides a solution to this problem with the recent introduction of the non-volatile, instant-on, AEC-Q100 qualified LatticeXP2 FPGA. Attend this webcast for detailed information on the LatticeXP2 FPGA and how it benefits automotive electronic designs.
FPGA Power Calculation Techniques ispLEVER Design Software -- This webcast provides an introduction to the use of FPGA design tools for power estimation, as well as which device features consume power and when. Lattice FPGAs and design tools will be used to illustrate several power calculation scenarios. This demonstration will help you to adopt a power verification strategy along with traditional simulation and static timing analysis.
Quick Timing Closure - Simulation & Debug of FPGA Designs ispLEVER Design Software 
and Lattice FPGAs 		9/15/08

Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help achieve timing closure faster. Don’t make the same mistake, identify and address problems earlier using a simulator and STA tools in concert. This webcast uses a Lattice reference design to show you how to use STA results to prepare a test bench, extract timing models from FPGA design tools, understand simulation results, and identify/trace problems before you program your Lattice FPGA. To wrap-up the verification process, designers can compare timing results against functional results to ensure design integrity.