May 2009

IP Support for the Recently-Released LatticeECP3 Family

Lattice IP cores are configurable design blocks that implement popular industry-standard functions, enabling users to design with maximum efficiency and deliver time-to-market solutions. Using the Lattice IPexpress tool in the ispLEVER software designers can create custom configurations of IP cores, fully integrate them into their design, and even test them in hardware before buying anything. 

The recently-announced LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The following IP cores now support the LatticeECP3 family, with many more coming soon.

Communication IP

• Common Public Radio Interface (CPRI)
  The Lattice Common Public Radio Interface (CPRI) IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeECP3, LatticeECP2M and LatticeSC/M FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information.  It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules. 
  
  Two CPRI core configurations are supported. The “basic” core configuration implements all of the capabilities required to support the physical layer of the CPRI specification, except specific requirements related to link delay accuracy. The “low latency” core configuration is equivalent to the basic configuration, but includes a modified SERDES/PCS interface that supports the ability to manage the variability in the absolute latency for data transmission through the core to meet the stringent CPRI link delay accuracy requirements.
  
• Tri-Speed Ethernet MAC
  The Lattice Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbps data rate) or the Fast Ethernet mode (10/100 Mbps data rate). Operation in either Gigabit mode or Fast Ethernet mode is selected by setting an internal register bit. The Tri-Speed Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface. 
  
• SGMII and Gigabit Ethernet PHY
  The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications. The PCS mode is pin selectable. This IP core may be used in bridging applications and/or PHY implementations. The Serial Gigabit Media Independent Interface (SGMII) is a connection bus for Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs) defined by Cisco Systems.
  

DSP IP

• Finite Impulse Response (FIR) filter
  A FIR Filter performs a convolution of an input data sequence with the filter's impulse response, which is stored in memory. The Lattice FIR Filter IP core is a widely-configurable, multi-channel FIR filter, implemented using high performance sysDSP blocks available in Lattice devices. In addition to single rate filters, the IP core also supports a range of polyphase decimation and interpolation filters.  The utilization versus throughput trade-off can be controlled by specifying the number of multipliers used for implementing the filter.  The FIR Filter IP core supports as high as 256 channels, with each having up to 2048 taps. 
• Distributed Arithmetic FIR (DA-FIR) Filter
  The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP Core implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms implemented in FPGA Look Up Table (LUT) or Embedded Block Memory (EBR) to efficiently support the sum-of-product calculations required to perform the filter function.  These techniques generate very area-efficient utilization of the FPGA LUTs while enabling savings of multiply-accumulate blocks (sysDSP) for other design logic. 
• Cascaded Integrator-Comb (CIC) Filter
  Cascaded Integrator-Comb (CIC) filters, also known as Hogenauer filters, are used to achieve arbitrary and large sample rate changes in digital systems. These filters are used as decimation or interpolation filters and can be efficiently implemented without multipliers, utilizing only adders and subtractors. Some applications that use the CIC filter include software designed radios, cable modems, satellite receivers, 3G base stations, and radar systems. Lattice provides a widely parameterizable CIC Filter that supports multiple channels with run-time programmable rates and differential delay parameters. 
• Numerically Controller Oscillator (NCO) 
  Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), offers several advantages over other types of oscillators in terms of accuracy, stability and reliability.  NCOs provide a flexible architecture that enables easy programmability such as on-the-fly frequency/phase.  NCOs are used in many communications systems including digital up/down converters used in 3G wireless and software radio systems, digital PLLs, radar systems, drivers for optical or acoustic transmissions, and multilevel FSK/PSK modulators/demodulators. Lattice provides a parameterizable NCO IP core that supports multiple channels and a Quadrature Amplitude Modulation (QAM) mode, in addition to other usual configurations. The resource utilization and performance trade-off can be tuned by configuring different parameters of the IP core to obtain the optimal Spurious Free Dynamic Range (SFDR) result. The Lattice NCO core offers a variety of memory reduction schemes and mechanisms for SFDR improvement. 

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