May 2008

Lowest-Cost JESD204 Support

Embedded high-speed SERDES channels in the LatticeECP2M FPGA enable support of the JESD204 serial ADC standard.

The JESD204 serial interface standard was necessitated by continuing advances made in data conversion technology. The standard addresses these evolving needs by providing a solution that requires less overall board interconnect than traditional source synchronous interfaces. This results in a lower-power, lower-cost and less noisy PCB that yields improved signal integrity and overall system performance. 

With LatticeECP2M FPGAs starting at less that $10 per device in high volume, Lattice offers the industry’s lowest-cost SERDES and DSP-equipped FPGA for serial data transfer and signal processing applications. Lattice has partnered closely with Linear Technology to provide early interoperation and joint demonstration platforms for the recently-announced LTC2274 16-bit, 105Msps, high-speed ADC. The joint platform utilizes a LatticeECP2M SERDES Evaluation Board, Lattice-developed JESD204 de-serializer reference design, and the Linear Technology DC1151 demonstration circuit. The setup is shown in the photo below.

JESD204 System Set-up

To Learn More

For the full reference design or to request a live demonstration, please contact your local Lattice distributor or sales representative.