May 2008

ispLEVER 7.1 Design Software Now Available

ispLEVER Design Tool Suite includes industry-first SSO Analyzer for SERDES design and new, upgraded synthesis and simulation tools.

ispLEVER 7.1 is the latest FPGA design software from Lattice. With a number of new functional and performance-enhancing features, ispLEVER 7.1 is better and easier to use than ever before.

An Industry First – SSO Analyzer

Simultaneous Switching Output (SSO) describes the noise caused by a large number of output drivers switching at the same time. Lattice has invented a new tool, the SSO Analyzer, which enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. 

Results are presented in a navigable HTML report and annotated onto the graphical Package View of the Design Planner tool. The SSO Analyzer brings design optimization to a new level.

Faster Design – Faster Results

The ispLEVER 7.1 design tools have been optimized and enhanced to bring an average 5% improvement to the top operating frequencies of designs, deliver up to 30% faster FPGA design compile times and support multi-processor-powered design compilation to achieve the fastest timing closure. These improvements decrease cost, speed timing closure and help FPGA designers deliver the best solutions more quickly.

Power Calculator Improvements

An enhanced Power Calculator enables FPGA designers to analyze and optimize power requirements early in their design. The Power Calculator includes an exceptionally user-friendly interface that enables power analysis at the block level, and examination of “what-if” scenarios by changing design environment variables. 

New Release of LatticeMico32 – Free, Open-Source Embedded Processor

A recent release of the LatticeMico32 embedded processor solution includes Linux O/S-based tools, VHDL language support (through VHDL wrappers of the Verilog IP) and added arbitration support. ispLEVER 7.1 seamlessly integrates the LatticeMico32 MicoSystem Builder into the standard design flow. The new arbitration support automatically selects the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated, enabling shared-bus or slave-side arbitration. This capability allows multiple master ports efficient access to multiple slave ports.

Lattice has also recently added the Micrium RTOS and the uClinux O/S to the portfolio. Inclusion with ispLEVER 7.1 marks the first full shipments that include the latest LatticeMico32 support.

Simulation from Aldec – Active-HDL Lattice Edition

ispLEVER 7.1 now includes the fast, comprehensive and feature-rich simulation environment – Active-HDL Lattice Edition (LE) from Aldec. You’ll now have access to simulation capabilities and features never before available with ispLEVER. Active-HDL LE is also dramatically faster for large designs. Active-HDL Lattice Edition features mixed language simulation of VHDL and Verilog and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. 

New releases of the downloadable ispLEVER Starter and ispLEVER Classic design tools will include Active-HDL Lattice Web Edition as well.

Aldec Active-HDL Lattice Edition

Synthesis from Synplicity – Synplify Pro for Lattice

The addition of Synplify Pro for Lattice brings a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Additional key features of Synplify Pro for Lattice include:

• HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code
• Mixed VHDL and Verilog synthesis support
• Automatic re-timing (balancing registers across combinatorial logic) for improved performance
• Automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA
• Windows, UNIX and Linux platform support

Synplify Pro for Lattice

ispLEVER Classic 1.1

ispLEVER Classic 1.1 supports the new ispMACH 4000ZE , the lowest-power CPLD ever available. With standby current as low as 10μA typical, and advanced features like Power Guard, per-pin pull-up/down, Bus Keeper control and performance to 260MHz, the ispMACH 4000ZE is the ideal solution for today’s power-sensitive portable applications.

ispLEVER Classic is the design environment for Lattice CPLDs and mature FPGAs.

To Learn More

To learn more about ispLEVER, including what’s new in this release, visit the Lattice website.