March 2010

LatticeECP3 FPGA Family Chosen as Finalist in EDN Innovation Awards Competition 

The LatticeECP3 FPGA family has been chosen from among hundreds of nominations as a Finalist in the 20th Annual EDN Innovation Awards competition. The Innovation Awards honor the people, products and technologies that have shaped the semiconductor industry over the past year.

“We received an impressive number of nominations for our 2009 Innovation Awards program,” said Rick Nelson, EDN editor-in chief. “Over the past several weeks, our editors faced the difficult task of narrowing down an impressive field of contenders and finding the freshest, most inventive, and undeniably outstanding nominations that were worthy of being named Finalists for EDN’s 2009 Innovation Awards. In the FPGA category, Lattice’s ECP3 FPGA family was one of the outstanding products our editors chose.”

The LatticeECP3 family defines a new mid-range, value-based class of FPGAs, not only by further reducing costs, but also by reducing total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. For example, to minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. By making careful design choices and minimizing die size, Lattice can offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices. With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications.

“We are honored to be named a Finalist in the EDN Innovation Awards competition, one of our industry’s most sought-after honors,” said Sean Riley, Corporate Vice President and General Manager of High Density Solutions. “Our ECP3 FPGA family already is among the most honored programmable logic products of 2009, and the large number of design wins we are experiencing is evidence that customers were eager for a new class of mid-range devices.”

EDN uses a combination of audience votes, balloting by the EDN Editorial Advisory Board and voting by EDN’s editorial staff to determine the ultimate winners. Voting will continue through March 19 on the EDN web site. EDN will present the awards April 26 at a ceremony during the Embedded Systems Conference in San Jose, CA.