March 2010View the new 5-minute LatticeECP3 CPRI Solutions Video to learn how CPRI frames are successfully transmitted in a complete REC to RE system using the LatticeECP3 FPGA with low latency variation.
The increasing need for low-power, low-cost platforms in wireless infrastructure equipment makes the LatticeECP3 FPGA the ideal choice for achieving the lowest overall cost.
The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with a low latency option in the physical coding sub-layer (PCS) for a smaller and cleaner CPRI implementation. Other features include DDR1/2/3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.
Watch this 5-minute video to:
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© Lattice Semiconductor Corporation 2012
