March 2009

ispLEVER 7.2 Offers New Reveal Triggering Additions

New triggering capabilities bring greater flexibility and power to the Reveal Logic Analyzer.

The Reveal Hardware Debugger in the new ispLEVER 7.2 design software offers the ability to define simple triggering conditions, as well as extremely complex triggers. The trigger is what determines when to start capturing data into the logic analyzer trace buffer which can then be used for debugging the FPGA functionality. Triggering in the Reveal software is based on the trigger unit and the trigger expression. A trigger unit is used to compare signals to a value, and a trigger expression is used to combine trigger units to form a trigger.

Trigger Units and Expressions

The trigger unit is used to compare a number of input signals to a value. A number of different operators are available for comparison and can be dynamically changed during analysis, along with the comparison value and the trigger unit name.

Trigger expressions are combinations of trigger units. Trigger units can be combined in combinatorial, sequential, and mixed combinatorial and sequential patterns. A trigger expression can be dynamically changed at any time. Each core supports up to 16 trigger expressions that can be dynamically enabled or disabled in the Reveal Logic Analyzer software. Trigger expressions support AND, OR, XOR, NOT, parentheses (for grouping), and THEN (for sequential operations) operators. Each part of a trigger expression, called a sequence, can also be required to be valid a number of times before continuing to the next sequence in the trigger expression by using a # (count) modifier.

New Trigger Expression Capabilities

In ispLEVER 7.2, Reveal adds two new trigger expression capabilities, the NEXT operator and the ## modifier. These new capabilities are closely related to the existing THEN operator and # modifier. The differences are listed below:

• THEN - Creates a sequence of wait conditions. For example, the following statement means “wait for TU1 to be true,” then “wait for TU2 to be true”. Reveal supports up to 16 sequence levels for each trigger expression.
  
  TU1 THEN TU2 
  
• NEXT - Creates a sequence of wait conditions, like THEN, except the second trigger unit must come immediately after the first. The following statement means “wait for TU1 to be true” then “on the next sample clock look for TU2 to be true”. If any part of the sequence is not true, the entire trigger expression resets and starts looking for the trigger again. This is extremely helpful for looking for a consecutive sequence, such as the header in a video data packet.
  
  TU1 NEXT TU2
  
• # (count) – Inserts a counter into a sequence. For example, the following statement means “wait for TU1 to be true” then “wait for TU2 to be true five times”. Note that this counter is non-consecutive. The five occurrences of TU2 can happen over any period of time.
  
  TU1 THEN TU2#5
  
• ## (consecutive count) – Inserts a counter into a sequence. Like # (count) except that the trigger units must come in consecutive sample clock cycles. That is, the trigger unit must be true on the sample clock immediately after being true on the previous sample clock and must not go false until after the count has been satisfied. If the count fails then the entire trigger expression resets and starts to look for the trigger again.

Examples

To better understand these differences, let’s look at a couple of examples. The following figure shows a sample clock, the signals in trigger unit 1 (TU1) and the signals in trigger unit 2 (TU2).

Figure 1. TU1 THEN TU2

For this example we have sent in the triggering options TU1 = 01 and TU2 = FF. Figure 1 is a match for the trigger expression “TU1 THEN TU2” and will produce a trigger. It is not a match for the expression “TU1 NEXT TU2” because TU2 = FF happens two sample clocks after TU1 = 01. To match the expression “TU1 NEXT TU2” it must occur on the next sample clock after the TU1 sequence is true.

Figure 2 shows a slightly different condition. TU1 and TU2 use the same settings (TU1 = 01 and TU2 = FF) but these now occur on different clocks.

Figure 2. TU1 NEXT TU2

Figure 2 is a match for the expression “TU1 NEXT TU2” since a match for TU2 occurs on the next sample clock after the match for TU1. Note also that this also is a match for the expression “TU1 THEN TU2” since the match for TU2 occurs one or more sample clocks after the match for TU1.

Figure 3 shows an example using a count. In this example TU1 and TU2 use the same settings as before.

Figure 3. TU1 THEN TU2#2

Figure 3 is a match for the expression ‘TU1 THEN TU2#2” since TU2 is matched twice after TU1 occurs. Figure 3 would not be a match for the expression “TU1 THEN TU2##2” since the two occurrences of TU2 are not consecutive.

Figure 4 shows an example using a consecutive count. This this example TU1 and TU2 use the same settings as before.

Figure 4. TU1 THEN TU2##2

Figure 4 is a match for the expression “TU1 THEN TU2##2” since TU2 is matched twice consecutively after TU1 occurs. Note that it would be a match for the expression “TU1 THEN TU2#2” also since TU2 is matched twice after TU1 occurs. However, Figure 4 would not be a match for “TU1 NEXT TU2##2” since TU2 is not first matched on the sample clock immediately following when TU1 occurs. In order to match the expression “TU1 NEXT TU2##2” the data would have to present as show in Figure 5. In this figure TU2 is matched on two consecutive sample clocks immediately following the sample clock where TU1 occurs.

Figure 5. TU1 NEXT TU2##2

The previous examples show the simplest conditions using the newest additions to the Reveal software triggering capabilities. An internal logic analyzer, such as the Reveal software, offers some significant advantages compared to an external logic analyzer but is constrained by resources inside the FPGA. The ability to accurately pinpoint the desired event in order to capture a smaller amount of data around that precise event is critical for an internal logic analyzer. The triggering options in the Reveal software are designed specifically for these requirements and offer the most advanced capabilities available today.

To Learn More

For more information about the ispLEVER design tool and what's new in ispLEVER 7.2, visit the Lattice website, or contact your local Lattice sales representative.