March 2008

Lattice FPGAs with Verilog Training Class

Dates: April 1-3, 2008
Location: Lattice Semiconductor Corporation, 2660 Zanker Road, San Jose, California
Skill Level: Basic to Intermediate
Cost: $1500
An iPod Nano will be raffled in class!

Do you have an upcoming Lattice FPGA design and need to brush up on Verilog Hardware Description Language? If so, the three-day Lattice FPGAs with Verilog training course is for you! Get to know the Verilog language and bridge the gap between the basic concepts in digital logic and related constructs used in Verilog-based design flows. There will be many examples provided to illustrate language features, including an introduction to modeling styles suitable for synthesis and verification.

In this course, you will:

• Learn which Verilog constructs to use for coding scenarios
• Understand the nuances of syntax and semantics
• Envision the synthesized logic expected from the HDL code
• Take designs through the entire Lattice FPGA flow
• Use advanced Lattice features such as clock constraints and floorplanning
• Write Verilog code to meet timing or utilization constraints

Course Outline

This is an intensive, interactive course which is approximately 50% lecture and 50% lab. Questions are highly encouraged.

• Day 1:
  - Verilog Design Flow with ispLEVER
  - Elements of Verilog Syntax
  - Verilog Operators
  - Dataflow Coding 
• Day 2:
  - Structural Verilog Coding 
  - Writing and Running Testbenches
  - RTL Coding for Combinatorial Logic
  - RTL Coding for Sequential Logic 
• Day 3:
  - Enhancing Performance 
  - Fine Tuning FPGA Devices

A more detailed course outline is available here.

To Learn More

For more information or to register for this course, contact:

Tom Wille
TM Associates, Inc.
503-656-4457
tw@tm-associates.com