Archive

2010

LatticeNEWS: February 2010

• LatticeECP3 DDR3 SDRAM Controller IP Core Released
  The industry's only DDR3 memory controller in a low-cost FPGA supports interfacing to both DDR3 devices and DDR3 DIMMs. Full story...
• New Examples Speed the Design-in of Fine-Pitch BGA Packages
  New PCB CAD resources were developed to help speed the adoption of Lattice fine-pitch (0.8 mm or less) ball pitch BGA packages that have emerged as the preferred solution to achieve high I/O density in the smallest system space. Full story...
• Digital Cameras Are a Snap with MachXO and ispMACH 4000ZE PLDs
• Get to Know the LatticeECP3 FPGA Family
• New Products Boost Lattice to a Profitable Fourth Quarter
• LatticeSC/M Package Conversions
• More...

LatticeNEWS: January 2010

• Happy New Year!
• LatticeECP3 is Electronic Products 2009 Product of the Year
  The LatticeECP3 FPGA family has been named Digital IC “Product of the Year” by Electronic Products magazine. Product of the Year recognition from Electronic Products is among the most prestigious and fiercely contested awards in the electronics industry. The award is held in such high regard due in part to the longevity of the competition and the selectivity of its editors. Full story...
• LCD-Pro Evaluation Kit Highlighted in FPGA Journal
  Lattice recently released the LCD-Pro Evaluation Kit a flexible image processing platform for FPGA families that includes board camera, display and intellectual property. The kit was recently the focus of a feature article published by FPGA Journal. Full story...
• Get a Head Start on Your Next PLD Design
• Read the Latest: "Analog for Nothing and Bits for Free: ADCs Using LVDS Buffers" and "I/O Initialization: Beware of Shark Fins!"
• More...

2009

LatticeNEWS: December 2009

• Quickly Evaluate the ispClock5400D With New Development Board
  The new ispClock5400D Evaluation Board provides an easy-to-use, low-cost platform to evaluate the performance characteristics of the ispClock5406D in-system differential clock distribution device. Full story...
• Lattice and Praesum Communications Offer the First Low-Cost FPGA with Serial RapidIO 2.1 Support%)
  apidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications. Full story...
• Lattice Ships 25 Millionth MachXO PLD
• Highest-Density LatticeECP3-150 FPGA Released to Production
• LatticeECP3 FPGA Family Wins Prestigious e-Legacy Awards Competition
• EDN China Honors LatticeECP3 FPGA Family and ProcessorPM Power Management Device
• New TechBites "Science and Technology Collaborative Community" is Blogging about Lattice
• More...

LatticeNEWS: November 2009

• New ispLEVER 8.0 FPGA Software Boosts Design Performance
  Lattice has released ispLEVER 8.0 with a major update to the support of the LatticeECP3 FPGA family as well as powerful enhancements to the LatticeMico32 based solution. Updated third-party synthesis and simulation tools are also included in this new version. Full story...
• "digitalTRX" RRH Solution from Lattice and Affarii Lowers Cost and Power
  Lattice and Affarii Technologies Limited, a solutions provider for networking and telecommunications applications, have developed a complete 3G/4G-based Remote Radio Head (RRH) solution for wireless infrastructure designers. This is the first time a full RRH solution has been made available using low power, low cost FPGAs that allows low power RRHs to be deployed without sacrificing flexibility or performance. Full story...
• Simplify System Control Designs with the MachXO Control Development Kit
• PAC-Designer 5.2 Supports New Power Manager II Devices and HDL Verification
• More...

LatticeNEWS: October 2009

• Lattice Delivers High-Speed Broadcast Video Connectivity Solution
  Lattice's complete platform for SMPTE applications provides a cost-effective and flexible approach to the challenges of multi-rate broadcast for SD, HD and 3G-SDI. Full story...
• New Evaluation Board Supports LatticeECP3 FPGAs
  The LatticeECP3 Serial Protocol Board allows designers to investigate and experiment with the features of the LatticeECP3 high-speed SERDES transceivers. Full story...
• Kick Start Your Next Design with Lattice Reference Designs
• Lattice and Epson Slash Costs for SERDES and Video Reference Clocks
• LatticeECP3 Continues to Receive Industry Honors
• More...

LatticeNEWS: September 2009

• LatticeECP3-150 FPGA Delivers Unprecedented Value for Wireless and Wireline Applications
  Lattice recently annouced availability of its highest-density LatticeECP3 device, the LatticeECP3-150. This low-power FPGA is ideal for high-volume, low-cost 3G basestation designs and other complex applications. Full story...
• Lattice Makes Consumer Electronics Design Fast and Easy
  New reference designs and development kits target low-power, space-constrained applications. Full story...
• Configurable Advanced Touch-Screen LCD Video Application Platform Now Available
• LatticeECP3 SERDES Supports SONET/SDH Protocol
• ispLEVER Classic Version 1.3 Update
• LatticeECP3 and ProcessorPM Nominated for EDN-China Innovation Awards
• LatticeFPGA Named a Finalist in e-Legacy Awards Competition
• More...

LatticeNEWS: August 2009

• Accelerate Time to Market for System Control Applications with New MachXO Control Development Kit
  The MachXO Control Development Kit provides a platform for rapidly prototyping system control applications such as temperature and current monitoring, power supply sequencing, reset distribution, fan control and more. Full story...
• $49 Kit is Versatile, Ready-to-Use Evaluation Platform for ProcessorPM
  The new ProcessorPM Development Kit enables high-speed system design with the ProcessorPM power management device, a programmable, single-chip solution for reset generation, watchdog timer and voltage supervision functions. Full story...
• Speed Development Time with New Reference Designs
• HV3 Module from Tachysséma for Image Processing and Embedded Applications
• Power Manager Family Highlighted in New EDN Article
• More...

LatticeNEWS: July 2009

• New MachXO Package Option Reduces Cost and Board Area
  Driven by an increasing need to minimize board space in telecom infrastructure, server, industrial and consumer applications, Lattice has introduced a new 0.8-mm pitch 256-ball Chip-Array BGA (caBGA) package for the popular MachXO PLD family. This provides designers with a broader range of package options for implementing cost-sensitive, board space constrained designs. Full story...
• ispLEVER 7.2 Service Pack 2 Available Now
  Service pack 2 for version 7.2 of the ispLEVER design tool suite is available now without charge for users with active design tool maintenance contracts. This update expands the breadth of the tool suite’s overall capabilities, and includes important updates for the mid-range LatticeECP3 and non-volatile LatticeXP2 FPGA families. Full story...
• Transceiver-Based IP Support for LatticeECP3 FPGAs
• Using Low-Cost Crystals with MachXO
• Hans Schwarz Joins Board of Directors
• More...

LatticeNEWS: June 2009

• New Automotive-Qualified Packaging for the LA-LatticeXP2 Family
  In response to increasing demand for small but powerful automotive solutions, Lattice has released low-cost, automotive temperature-qualified packaging for the non-volatile LA-LatticeXP2 FPGA family. The new 132-ball csBGA package enables designers to squeeze processing power in the tightest of automotive system form-factors. Full story...
• Industrial Temperature-Qualified LatticeXP2 Devices Released to Volume Production
  Lattice has released an industrial temperature-certified version of the popular LatticeXP2 FPGA family. Available in low-cost, small footprint BGA or QFP packaging, the LatticeXP2 now offers an industrial temperature option, in addition to standard commercial and automotive temperature ranges. Full story...
• DSP IP Support for LatticeECP3 FPGAs
• Multi-Channel DDC/DUC Reference Design for 4G Communication Systems
• More...
  

LatticeNEWS: May 2009

• New "Processor Power Manager" Reduces the Cost of Microprocessor Support
  New ProcessorPM devices integrate the functions of separate power management ICs used in microprocessor and DSP designs; improved monitoring accuracy increases design reliability. Full story...
• IP Support for LatticeECP3 FPGAs
  The recently-released LatticeECP3 FPGA famly is now supported by a host of IP cores, with many more coming soon. Full story...
• LatticeECP2 Has "Starring Role" in New Reference Design
• Huawei Technologies Honors Lattice for its Customer Support
• More...
  

LatticeNEWS: April 2009

• LatticeMico32 System Now Supports "Inline Memories" for LatticeMico32-Based Platforms
  The LatticeMico32 CPU can now be connected to on-chip memory via the LatticeMico32 dedicated Processor Local Bus. Full story...
• Differential Sensors Provide Superior Accuracy for Supervisory and Timing Applications
  Differential sensing by the Power Manager II device family provides highly-accurate voltage supervision and DC/DC trim circuits that traditional discrete ICs cannot achieve with single-ended inputs. Full story...
• SOHO VOIP Solution: Intel/Lattice HSS-to-PCI Express Bridge
• More...
  

LatticeNEWS: March 2009

• New 5-Minute Videos Feature Lattice Products in Action
  Several new videos provide a hands-on look at the new LatticeECP3 FPGAs, MachXO Mini Development Kit, 7:1 LVDS interface, PCI Express and more. Full story...
• ispLEVER 7.2 Offers New Reveal Triggering Additions
  New triggering capabilities bring greater flexibility and power to the Reveal Logic Analyzer. Full story...
• LatticeXP2 7:1 LVDS Video Reference Design and Demo Kit Available Now
• Platform Management Using Low-Cost, Non-Volatile MachXO PLDs
• Tuning Power Efficiency
• Tradeshow Recap: Embedded World Conference 2009, Nuremberg Germany
• More...
  

LatticeNEWS: February 2009

• Letter from the Editors
• New LatticeECP3: Industry’s Lowest-Power, Highest-Value FPGA in Production Today
  Utilizing an ultra low power, cost-optimized 65-nm process FPGA architecture, LatticeECP3 extends the functionality of prior generation families to new levels and provides enhanced features at a fraction of the power consumption and cost of competing devices. Full story...
• Accelerate Your Design Time with New MachXO Reference Designs and Mini Development Kit
  15 new reference designs and a new $59 Mini Development Kit are ideal for prototyping high-volume, cost-sensitive low-density applications. Full story...
• Lattice Announces Ultra-Low Phase Noise, Zero-Delay Buffer Clock Family
• ispLEVER 7.2 Service Pack 1 Available Now
• PAC-Designer 5.0 Ready for Download
• Lattice Ships 15 Millionth MachXO PLD
• Reliability Monitor Report
• More...

LatticeNEWS: January 2009

• New ispLEVER 7.2 Design Tool Includes Clock Domain Analysis Report
  The new Clock Domains Analysis section of the TRACE report is just one of the handy new features included with Lattice's recently-released ispLEVER 7.2 design software. The information contained in this report can be critical to verifying that your design is correctly constrained. Full story...
• ispPAC-POWR607 Power Manager II Device Integrates Multiple Discrete ICs
  As engineers are pressured to cut costs and improve the reliability of circuit boards, an often overlooked opportunity is to reduce the number of components used for power monitoring. The ispPAC-POWR607 is an ideal solution that combines reset generation, watchdog timer (WDT) and voltage supervisor ICs into a single device. Full story...
• LatticeECP2M FPGA Family Wins Prestigious EDN China Award
• More...

2008

LatticeNEWS: December 2008

• ispMACH 4000ZE Devices Just Got Smaller
  Lattice's low-power ispMACH 4000ZE CPLD is now available in ultra chip scale BGA packages that offer a 36% smaller footprint - perfect for space-constrained, hand-held applications. Full story...
• ispClock5300S: Revolutionizing PCB Clock Distribution
  The ispClock5300S provides system engineers a way to standardize a PCB clock solution across products. Full story...
• Lattice Introduces SERDES Framer Interface, Level 5 (SFI-5) IP Core
• More...

LatticeNEWS: November 2008

• ispLEVER 7.1 SSO Analyzer - An Industry First!
  Simultaneous Switching Output (SSO) analysis during the course of I/O planning can help mitigate noise conditions early in the design flow, thus saving time and preventing reliability issues later on. The Lattice SSO Analyzer is a unique tool to assist designers in performing this vital analysis. And currently, such a tool for FPGA design is only available from Lattice. Full story...
• Low-Cost MachXO Starter Evaluation Board Offers Convenient Design Platform
  This ready-made platform for the MachXO256 includes an AC adapter and download cable, all for $99! Full story...
• ispMACH 4000ZE Perfect for Low-Power, Space-Constrained Hand-Held Applications
• IP Suites Offer a Total IP Solution for Less
• Reliability Monitor Report
• More...

LatticeNEWS: October 2008

• Video: New Low-cost PCI Express Development Kit
  Watch this 5-minute video and learn how easy it is to implement PCI Express designs using LatticeECP2M FPGAs. See how to get to working hardware in less than 30 minutes. Full story...
• PCI Express Development Kit: Implement PCI Express Links in Under 30 Minutes!
  New low-cost LatticeECP2M Development Kit enables rapid PCI Express system design - 30 minutes to demo, 2 hours to design validation. Full story...
• Accelerate Display Interface Design with 7:1 LVDS Reference Design
• Flexible Image Processing Platform for LatticeECP2 FPGAs
• Wireless Solutions Brochure Available
• More...

LatticeNEWS: September 2008

• ispLEVER 7.1 Service Pack 1 Available Now
  This important upgrade for ispLEVER 7.1 software includes new 3rd party synthesis and simulation tools, integration of the ORCAstra configuration utility, expands Reveal Logic Analyzer support to the Linux platform, adds support for new automotive temperature grade LatticeXP2 non-volatile FPGAs, and much more.  Full story...
• Scatter-Gather DMA Demo for Scaling and Measuring PCI Express Performance
  New demo enables measurement of high-throughput PCI Express applications with non-contiguous memory systems.  Full story...
• Improved SPI4.2 Interface Offers Numerous Benefits
• PAC-Designer Design Tool Now Supports Automotive Versions of Power Manager II Devices
• More...

LatticeNEWS: August 2008

• Four Popular ispLeverCORE IPs are LatticeMico32 Compatible
  The LatticeMico32 is an open source 32-bit RISC processor that is generated by the Mico System Builder (MSB) environment, which may be freely downloaded from the Lattice website. Lattice has been increasing the number of paid-for IP cores that seamlessly integrate with the LatticeMico32 in the MSB.  Full story...
• ispMACH 4000ZE Ideal for Small, Low-Power, Low-Cost Portable Products
  New CPLD family features industry's lowest static power, and standby current as low as 10uA, in ultra-small, space-saving packages. Full story...
• ispLEVER Classic 1.2 Available Soon
• Verilog Training Classes
• More...

LatticeNEWS: July 2008

• LatticeXP2 Moves to the Driver's Seat
  On June 30th, Lattice announced that automotive versions of its non-volatile, 90nm Flash-based LatticeXP2 FPGAs have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council.  Full story...
• New Mixed-Language Flow and Platform Support for ispLeverCORE IP Cores
  Design flow improvements ease adoption of IP core solutions. Full story...
• Active-HDL Simulator Training Available
  
• Lattice and the Road to 100G Alliance at NXTcomm08
• More...

LatticeNEWS: June 2008

• New Board for Ultra Low Power ispMACH 4000ZE CPLD
  The ispMACH 4000ZE Evaluation Board is a compact, efficient and low-cost platform designed to help you evaluate the ispMACH 4000ZE technology, learn the device features and operation, and prototype your own design. Full story...
• Modular ATCA FRU Payload Power Management Architecture
  The ispPAC-POWR1220AT8 Power Manager device is the key to a new approach in ATCA power management, providing increased flexibility and fault coverage. With the POWR1220, you not only get a more flexible and robust solution, you can also reduce your time-to-market and reduce cost. Full story...
• Lattice Goes Wireless
  
• Synthesis Handshaking Improved in ispLEVER 7.1
• Multifunction Secure Digital Design Made Simple
• More...

LatticeNEWS: May 2008

• New ispMACH 4000ZE Family Uses Ultra-Small, Space-Saving Packages
  On April 28th, Lattice announced its new, ultra low power CPLD, the 1.8V ispMACH 4000ZE family. This second-generation in-system programmable CPLD family is ideal for low-power, high-volume portable applications, with typical standby current as low as 10µA. Full story...
• ispLEVER 7.1 Design Software Now Available
  ispLEVER Design Tool Suite includes an industry-first SSO Analyzer for SERDES design and new, upgraded synthesis and simulation tools, making ispLEVER better and easier to use than ever before. Full story...
• Digital Power Management for Analog Power Supplies
  
• Lowest-Cost JESD204 Support
• Microcontroller Obsolescence Solution
• More...

LatticeNEWS: April 2008

• Entire LatticeXP2 Family Shipping in Volume
  Developed using the industry's most advanced non-volatile FPGA technology, a 90nm embedded Flash process, the LatticeXP2 devices provide the “instant-on” and reduced footprint benefits of earlier non-volatile Lattice devices, while also enhancing design security, RAM back-up and live update capabilities. Full story...
• LatticeMico8 Receives a Makeover. And It’s Still Open Source.
  Enhancements have been made to increase code size and ease of programming. Full story...
• Improved PLDA XpressLite Solution Simplifies Evaluation and Design
  
• Design Consulting Program Expands
• More...

LatticeNEWS: March 2008

• LatticeXP2 Non-Volatile FPGA Devices Released to Production
  The 17K LUT LatticeXP2 –17 device, one of five members of Lattice's third-generation non-volatile LatticeXP2 FPGA family, has been fully qualified and released to volume production. Full story...
• uClinux for the LatticeMico32 Accelerates Embedded Development
  Lattice has expanded its commitment to open source embedded system design by releasing an implementation of the uClinux Operating System targeted for the LatticeMico32 embedded soft core processor.Full story...
• Lattice Automotive Offering Expands with 2008 Model Introduction
• Avoid the Pitfalls of Reset Generator and Voltage Supervisor Selection
• More...
  

LatticeNEWS: February 2008

• Power Manager II Moves Into the Fast Lane
  Lattice has released automotive versions of its second generation Power Manager II family. The popular ispPAC-POWR1014 and ispPAC-POWR1014A have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council. Full story...
• LatticeXP2 Chosen as "Hot 100" Product
  The third-generation, non-volatile LatticeXP2 FPGA family was recently recognized as one of the “Best and Brightest” products of 2007 by EDN Magazine. Full story...
• Low-Cost Serial RapidIO Solution
• More...

LatticeNEWS: January 2008

• ispLEVER 7.0 Service Pack 2 Now Available
  New 3rd party Synthesis versions, Power Calculator tool enhancements and concurrent LatticeMico32 System tools release support VHDL design and the Linux operating system. Full story...
• Low-Cost, FPGA-Based ADC Interface Reference Design Solution
  The recently-announced LatticeECP2/M FPGA interface reference design supports the Texas Instruments ADS6000 family of analog-to-digital converters, and delivers exceptional performance and value. Full story...
• More...

2007

LatticeNEWS: December 2007

• Entire 90nm LatticeECP2M FPGA Family Released to Production
  All members of the LatticeECP2M family are now shipping in volume. Full story...
• IEEE 1588 for Industrial Ethernet in IP or ASSP
  Lattice and Oregano Systems partner to deliver a clock synchronization solution that meets the IEEE 1588 standard. Full story...
• New Throughput Demo Measures PCI Express Performance
• Synplify® DSP Now Supports LatticeECP2M and LatticeXP2 FPGAs
• More...

LatticeNEWS: November 2007

• Affordable FPGA-Based SMPTE SDI Solution Demonstration
  Lattice's low-cost LatticeECP2M FPGA, and Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core make a compelling video solution. Lattice has developed a complete system to demonstrate compliance to SMPTE standards and highlight various aspects and modes of the solution.  Full story...
• New LatticeMico32 Demo with DDR Memory and VGA Monitor
  This new demo brings together the LatticeMico32 soft processor with DDR2 memory controller IP and VGA monitor IP on the LatticeECP-based LatticeMico32/DSP Development Board.Full story...
• Lattice and Dune Networks to Develop SPAUI-Based Network Solutions
• Helion Vision Selects LatticeXP2 for Next Generation Camera Modules
• More...

LatticeNEWS: October 2007

• Lattice Releases Bridging Solution for Switched Ethernet Applications
  Trying to hook up your Network Processor to an Ethernet switch, but frustrated by high IP licensing fees, high power consumption and large FPGA footprints? Fear not, the X2S4 solution is here. Full story...
• ispLEVER Service Pack 1 Adds Full LatticeXP2 Support and More
  A valuable update to the ispLEVER 7.0 FPGA design software is now available for all licensed ispLEVER users. Service Pack 1 includes new support for LatticeXP2-8 and LatticeXP2-30 FPGAs and numerous other productivity enhancements. Full story...
• New Industry Alliances for Interoperability and Hypertransport
• More...

%link,01-05-02-06,LatticeNEWS: September 2007%)

• Lattice FPGAs Ideal for High-Security Applications
  In today's complex systems, FPGAs are increasingly used to replace functions traditionally performed by ASICs and even microprocessors. Ten years ago, the FPGA was at the fringe of most designs; today it is often at the heart. Consequently, FPGA design security has become an increasingly important topic of discussion for designers. Full story...
• Open Source Drives Lattice Soft Microprocessors
  Lattice has introduced an open source soft microcontroller, the LatticeMico8, and an open source soft microprocessor, the LatticeMico32, targeted towards FPGAs and optimized for Lattice FPGAs. Unlike traditional open source software licenses that require derivative works to be open source, Lattice recognizes that devices that use open source microprocessors need to be proprietary. Full story...
• Configure Lattice MACO with IPexpress
• More...

LatticeNEWS: August 2007

• HyperTransport Supports Up to 1600Mbps in LatticeSC/M FPGAs
  The LatticeSC/M FPGA families now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and memory interfaces are implemented using the LatticeSC/M families' innovative PURESPEED I/O technology. Full story...
• Twisted Pair Cable High-Speed Serial Transmission with LatticeSC/M FPGAs
  The use of twisted pair cabling for backbone and intra-platform interfaces is becoming increasingly common. Relatively inexpensive and ubiquitous cabling and cable connectors are available that comply with the TIA/EIA-568-A Commercial Building Wiring Standard.  Full story...
• Standardized Programmable Power Management
• Lattice-PLDA Partnership Builds PCI Express Connectivity
• New ispClock5312S Evaluation Board Supports Versatile ispClock Device
• More...

LatticeNEWS: June 2007

• New LatticeXP2 FPGA Family Doubles Density and Cuts Cost
  On May 29th Lattice announced the availability of its third generation non-volatile FPGAs, the LatticeXP2 family. With enhanced capabilities, the LatticeXP2 family doubles maximum logic capacity to 40K Look-Up Tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%. Full story...
• ispLEVER 7.0 Design Software Now Available
  It’s official: ispLEVER 7.0 packs some serious new silicon support, greatly improved performance metrics, and some dynamite new features and enhancements. Full story...
• More ...

LatticeNEWS: January 2007

• New 90nm LatticeECP2M FPGAs Offer Embedded SERDES
  Lattice has announced the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family also has been developed on advanced 90nm CMOS technology utilizing 300mm wafers. Full story...
• Ultra Low Cost Power Management Solution
  Recently, Lattice announced the addition of the programmable, ultra low cost ispPAC-POWR607 device to its second generation Power Manager II product family. The new devices achieve a sub-$1.00 price point in high volume, targeting many cost-sensitive power management applications in consumer markets such as LCD TV, automotive multimedia systems, GPS receivers, Multimedia Terminal Adapters and set-top boxes. Full story...
• ispLEVER 6.1 Design Software Now Available
• LatticeSC/M25 Goes to Full Production
• More...

2006

LatticeNEWS: August 2006

• Programmable SPI4.2 Solution for LatticeECP2 FPGAs
  The Lattice SPI4.2 solution targets the LatticeECP2™ FPGA and is the only programmable solution based on a low cost FPGA fabric that can operate at the full 10Gbps line rate.   Full story...
• Accelerate Your Time to Market with Low Cost Lattice Automotive Devices
  Lattice is in high-gear to achieve TS-16949 Automotive certification by Q4, 2006. In addition, Lattice is expanding its commitment to the automotive marketplace with the release of the AEC-Q100 qualified Lattice automotive product families, LA-MachXO and LA-ispMACH4000V. Full story...
• Lattice Expands ispClock5300S Family
• ispLEVER 6.0/SP1 Adds 90nm FPGA Support and More
• More...