June 2011FPGA IP Cores Provide Seamless Redundancy With Zero Time to Recovery from Network Failures
Lattice and Flexibilis Oy have announced availability of the Flexibilis Ethernet Switch (FES) IP cores. The triple speed (10Mbps/100Mbps/1Gbps) FES IP cores operate on Ethernet Layer 2 and can switch with Gigabit forwarding capacity per port. Both Gigabit Fiber optic and Gigabit twisted pair copper Ethernet interfaces are supported. Quality of service is supported with up to four queues per port. These Ethernet switch IP cores, available in five versions, vary in their number of ports and functionality:
• 6-port FES – HSR (QuadBox)
• 4-port FES – HSR (End-node / RedBox)
• 8-port FES
• 4-port FES
• 3-port FES
The FES – HSR IP cores enable designers of smart grid substation automation and industrial networking applications to immediately and confidently apply the emerging High-availability Seamless Redundancy (HSR) protocol using LatticeECP3 FPGAs. This IEC protocol (IEC62439-3) provides cost effective redundancy with no single point of failure and zero time to recovery in case of failure. The HSR protocol is typically used in applications where time synchronization is also needed. Therefore IEEE1588 Precision Timing Protocol (PTP) end-to-end transparent switch functionality is also included. The FES-HSR IP cores are applicable across a range of applications that demand high availability, Gigabit-class data transfer capacity and sub-microsecond accuracy. Target applications include smart grid substation automation and networked industrial automation gear, as well as high availability network equipment.
4-Port FES - HSR (End-node/RedBox) IP Core for the LatticeECP3 FPGA
Provides Zero-Time Recovery from Network Failures
The FES IP cores are equipped with IEEE 1588 version 2 end-to-end transparent switch functionality, which significantly improves the ability to resist the degradation of clock information quality in larger networks. This ability is critical in meeting the strict clock quality requirements of future mobile cellular network base stations, wireline access, electrical substation and industrial automation and other control and measurement applications. Nanosecond-class accuracy in clock transfer enables backup or replacement of GPS-based synchronization in critical applications. This feature makes the FES IP cores suitable for applications such as mobile backhaul routers, cell site routers and industrial automation products.
The LatticeECP3 FPGA family is comprised of the lowest power, SERDES-enabled FPGAs in the market today. The family’s five FPGAs offer standards-compliant, multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive video camera and display, wireline, and wireless infrastructure applications.
Headquartered in Tampere, Finland, Flexibilis Oy (Inc.) is a provider of networking equipment and technologies for wireless and wired applications. Flexibilis employs high-end technologies, including extensive use of programmable hardware.
For pricing or additional technical information, please visit the Flexibilis website or contact Flexibilis Oy at contact@flexibilis.com.
© Lattice Semiconductor Corporation 2012
