June 2010

Low-Cost Brevia Development Kit Accelerates Application Development for LatticeXP2 FPGA Family

On June 7, Lattice released the LatticeXP2 Brevia Development Kit along with 28 silicon-proven reference designs to empower designers across various markets to quickly learn about the versatility of LatticeXP2 FPGAs and rapidly develop solutions for various applications including general purpose I/O expansion, video image signal processing, interface bridging and control functions.

The Kit is available for a special promotional price of $29 until August 31, 2010.

The LatticeXP2 Brevia Development Kit

The LatticeXP2 Brevia Development Kit includes the following:

• Compact evaluation board featuring the LFXP2-5E-6TN144C device, 2Mbit SPI Flash and 1Mbit SRAM memory, expansion headers, SPI interfaces, several LEDs and user switches
• Preloaded Brevia WISHBONE UART design allows designers to test SPI, UART, SRAM interfaces and the 8-bit LatticeMico8 microcontroller within minutes. They can then build their own designs using the free downloadable reference design source codes, implementing these features in less than an hour.
• Various reference designs and free ispLEVER Starter design software which can also be downloaded from the Lattice web site.
• Parallel JTAG cable for device programming and a serial RS232 cable for host interface
• AC power adapter
• QuickSTART documentation

The LatticeXP2 Brevia Evaluation Board

28 New Reference Designs Target Resource-Intensive Applications

A comprehensive set of 28 new reference designs has been optimized for the LatticeXP2 FPGA family. These designs serve as a starting point for designers and cover a wide range of high-density applications. Each reference design includes a web page that provides a brief overview of the design, design documentation and source code. The reference designs can be downloaded from the web pages free of charge.

• Controller and Display
  
  • LatticeMico8 Microcontroller
  • LatticeMico8 to WISHBONE Interface Adapter
  • LCD Controller (Wishbone Compatible)
• Serial Connectivity
  
  • SPI WISHBONE Controller
  • WISHBONE UART
  • UART
  • Control Link Serial Interface
  • HDLC (High-level Data Link Control) Controller
• Bus Connectivity
  
  • PCI/WISHBONE Bridge
  • PCI to NOR Flash Interface
  • PCI Target 32-bit/33MHz
  • LPC Bus Controller
  • I2C Master Controller
  • I2C Slave / Peripheral
  • I2C Controller for Serial EEPROMs
  • I2C Master with WISHBONE Bus Interface
  • I2C Extender
• Memory Controllers
  
  • SD Flash Memory Controller
  • NAND Flash Memory Controller
  • Compact Flash Controller
  • SDRAM Controller (Advanced)
  • Fast Page Mode DRAM Controller
• System Control, Management, and Debug
  
  • Digital PWM Fan Controller
  • Power Manager Fault Logger
  • Simple Delta-Sigma ADC
  • GPIO/Interrupt Expander
  • BSCAN1 – Multiple Boundary Scan Port Adressable Buffer
  • BSCAN2 – Multiple Boundary Scan Port Linker

About the LatticeXP2 FPGA Family

The LatticeXP2 family combines a Look-up Table (LUT)-based FPGA fabric with Flash non-volatile cells in Lattice’s flexiFLASH architecture. The flexiFLASH approach provides benefits such as instant-on operation, a small footprint, on-chip storage with FlashBAK embedded block memories, serial TAG memory and the highest design security. LatticeXP2 devices also support live updates with Lattice’s unique TransFR technology, 128-bit AES design encryption and dual-boot technologies. The family provides five devices ranging between 5K and 40K LUTs in a wide variety of packages including a tiny 8mmx8mm csBGA.

Visit the Lattice web site for full details on the LatticeXP2 Brevia Development Kit, reference designs, and ready-made SoC demos.