June 2010

LatticeECP3 JESD204A Interoperability Testing with CGV High-Speed Converters from NXP Semiconductors

The JESD204A standard describes a serialized interface between data converters and logic devices. While the JESD204 specification supports single lane links, the JESD204A specification improves on that with support for multiple data converter channels or lanes to be bonded synchronously.

NXP Semiconductors is the first supplier to offer a JESD204A-compliant solution for high-speed ADCs and DACs. It recently announced the availability of two low-cost, low-power demonstration boards for its Convertisseur Grande Vitesse (CGV™) high-speed data converter (ADC/DAC) family, based on the LatticeECP3.

• The first demo board features the NXP ADC1413D and the LatticeECP3 device. This board is available now and is priced at $299.
• The second board features the NXP DAC1408D and the LatticeECP3 device. This board is expected to be available in September 2010 and is priced at $299.

Please contact NXP for more information on the boards.

NXP CGV High Speed Data Converters

The NXP CGV high-speed data converters are fully compliant to the JESD204A standard. These data converters deliver a number of additional benefits over and above standard JESD204A implementations including:

• Transmitter rate of up to 4.0 Gbps vs. the standard rate of 3.125 Gbps.
• Transmitter reach up to 100 cm vs. the standard reach of 20 cm.
• Multi Device Synchronization (MDS) for up to 16 DAC1408D series of D/A Converters to enable LTE MIMO base station and other advanced multi-channel applications.

Lattice JESD204A IP Core

The Lattice JESD204A IP core supports both a receive (Rx) core (ADC-to-FPGA direction) and/or a transmit (Tx) core (FPGA-to-DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.

LatticeECP3 Interoperability Testing with NXP ADC

Interoperability testing of the Lattice JESD204A Rx IP core was performed between a LatticeECP3 device on a LatticeECP3 I/O Protocol Board connected to an NXP ADC1413D on an NXP evaluation board. After establishing the connection and resetting and configuring the NXP board, the status outputs of the Lattice Rx IP core were checked to verify that the core could frame on the JESD204A link data from the NXP ADC device.

Next, the NXP board sourced various test patterns to the Rx IP Core. The Reveal Logic Analyzer was connected to the Rx IP core user outputs to verify that the data patterns sourced from the NXP board were successfully received by the Rx IP core, and that all lanes remained in alignment.

Interoperability test setup

Learn more about the Lattice JESD204A IP core and the interoperability test, visit the Lattice web site or download the JESD204A IP Core User's Guide.