June 2010

DVB-ASI IP Core Released

Digital Video Broadcasting (DVB) is a suite of open standards for digital television. DVB via Asynchronous Serial Interface (or DVB-ASI) is designed to transport MPEG-2 video streams over cable media, primarily for television applications, at up to 270 Mbps. The electrical implementation of DVB-ASI is similar to Serial Digital Interface (SDI).

DVB-ASI is based on a layered architecture, with each layer doing a specific electrical or logic function.

• Layer 0 is the physical layer that includes the amplifier, impedance matching and the connectors that ensure electrical compliance to the interface.
• Layer 1 is the coding layer that includes the 8b10b encoding/decoding, comma character insertion/deletion, clock/data recovery and parallel-to-serial/serial-to-parallel conversions.
• Layer 2 deals with higher-level functions such as creating transport stream packets and Reed-Solomon encoding/decoding.

 

 

The Lattice DVB-ASI IP core along with LatticeECP3 SERDES/PCS implements Layer 1 and a part of the Layer 2 functionality of the DVB-ASI interface.

Features:

• Configurable Tx FIFO supporting independent Layer 2 transmit clock
• Configurable Rx FIFO supporting independent Layer 2 receive clock
• Automatic start of packet comma insertion in the transmit side
• Rate-matching comma insertion in the transmit side
• Handshake signals for sync and data valid for transmitter and receiver
• Tx and Rx FIFO full indicators
• Rx sync byte indicator for identifying start-of-packet
• Optional configurable almost full and almost empty indicators for the FIFOs
• Matching port names for seamless connection with LatticeECP3 SERDES/PCS
• Layer 2 functions including lock, sync byte, packet size, runt and giant indicators

DVB-ASI Sample Designs

The IP core comes with a self-checking top-level design that includes the IP core block, LatticeECP3 SERDES block, DVB-ASI traffic generator block and a data comparison block. The test bench instantiates the sample design and applies clock and other control signals to it. The demo designs generated along with the IP core are in plain Verilog and provide an example of a complete DVB-ASI Tx/Rx system using the IP core, SERDES and other test logic.

Two sample designs are provided with the generated DVB-ASI IP core: 

• Single-Channel Demo Design: The single-channel DVB-ASI demo design can be used to test the transmit  and receive logic of the IP core without the help of an external DVB-ASI source or sink. It includes a random data generator module, LatticeECP3 SERDES/PCS, a character LCD display interface and other test logic, in addition to the IP core.
• Two-Channel Demo Design: The two-channel demo design is designed to test and demonstrate the functionality of two DVB-ASI channels operating within the same SERDES quad.

 

 

Evaluation Boards

The DVB-ASI IP core can be evaluated with the LatticeECP3 Video Protocol Board.

 

 

Software Support

The DVB-ASI IP core can be generated using the Lattice IPexpress tool. It is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. The GUI-based tool allows designers to specify various parameters to generate the IP core.

 

To Learn More

For further information about the DVB-ASI IP core, visit the Lattice web site.