June 2010With the formalization of the JTAG standard as IEEE1149.1 and its subsequent adoption in ICs, Boundary Scan Testing (BSCAN) has become widely adopted in testing circuit boards. However, on larger circuit boards such as those typically found in telecom, infrastructure, and industrial markets, designers face multiple challenges in detecting and isolating faults, reducing test times, physical routing while balancing skew, voltage translations and addressing special CPU needs.
BSCAN control has traditionally been implemented using ASSPS, however, the problem with using ASSPs is that they are more expensive, have fixed voltage levels and number of ports, and do not provide any customization.
A PLD-based BSCAN control solution enables designers to reduce board cost and simplify board layout by eliminating the need for voltage translators and clock buffers, reducing test times and offering greater system integration by incorporating custom logic within the same IC.
MachXO PLDs offer an improved solution by providing:
MachXO PLD BSCAN Control Application Example
By using Lattice’s Multiple Boundary Scan Port Addressable Buffer (BSCAN1) and Multiple Boundary Scan Port Linker (BSCAN2) reference designs, designers can rapidly prototype BSCAN control applications with the MachXO Control Development Kit.
For more information about the MachXO PLD family, or the BSCAN1 and BSCAN2 reference designs, visit the Lattice website or contact your local Lattice sales representative.
© Lattice Semiconductor Corporation 2012
