June 2009

Multi-Channel DDC/DUC Reference Design for 4G Communication Systems

Lattice recently released a Multi-Channel Digital Down/Up Converter (DDC/DUC) reference design. While this design was tested for a WiMAX (Worldwide Interoperability for Microwave Access) configuration, it is broadly applicable to various 4G standards, such as LTE.

Digital Up Converter (DUC)

A Digital Up Converter translates the base band signal to a higher frequency Intermediate Frequency (IF) band. This is done by first up-sampling the base band signal to the required sampling frequency and then mixing it with a high-frequency carrier. A functional block diagram of the DUC is shown below.

DUC Block Diagram

Digital Down Converter (DDC)

A Digital Down Converter performs the reverse function of that of a DUC. It converts a signal from the Intermediate Frequency (IF) band to the base band. The DDC is built using a structure similar to the DUC, but it uses decimation filters instead of interpolation filters and they are connected in the reverse order of the DUC. A functional block diagram of the DDC is shown below.

DDC Block Diagram

Multi-Channel (MC) DDC/DUC

Wireless base station manufacturers continue to seek ways to add value and performance while increasing differentiation. Transmit/receive functionality has become an area of focus as designers attempt to address the need to move data from very high frequency sample rates to chip processing rates. DUCs and DDCs are used for this purpose and typically include frequency shifting using mixers, in addition to sampling rate conversion.

There is a growing need for device reusability and flexibility in DDC/DUC design to support several communications standards and different spectrums of input sample frequencies. Lattice’s Multi-Channel DDC/DUC reference design for the LatticeECP2M FPGA family helps meet these performance and flexibility requirements while delivering power and cost savings. It is broadly applicable to various 4G standards such as LTE and WiMax. This reference design was specifically tested for a WiMAX configuration.

The MC DUC and MC DDC are implemented using a scheme that results in the best area utilization on FPGA devices. Since the filter chains in both I and Q channels are identical, the same set of filters can be time-multiplexed to accommodate both channels. The MC DUC and MC DDC reference designs are built using the Lattice Numerically Controlled Oscillator version 2.3, FIR Filter version 4.0 and Distributed Arithmetic FIR (DA-FIR) Filter version 2.0 IP cores.  The MC DUC/DDC functional block diagrams are shown below.

MC DUC Block Diagram

MC DDC Block Diagram

To Learn More

The user's guide, Multi-Channel Digital Up/Down Converter for WiMAX Systems, includes details on this reference design. The reference design can be downloaded from the Lattice website.