June 2009

DSP IP Support for LatticeECP3 FPGA Family

The recently-announced LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high-density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. Lattice has released an extensive portfolio of DSP (Digital Signal Processing) IP (intellectual property) cores to support the LatticeECP3 family.  

Lattice IP cores are configurable design blocks that implement popular industry-standard functions, enabling users to design with maximum efficiency and deliver time-to-market solutions. Using the Lattice IPexpress tool in the ispLEVER software, designers can create custom configurations of IP cores, fully integrate them into their design, and even test them in hardware before buying anything.

The following DSP IP cores now support the LatticeECP3 family, with many more coming soon.

CORDIC

CORDIC (COordinate Rotation DIgital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric functions and convert polar co-ordinates to artesian and vice versa. It is an iterative method that requires simple arithmetic operations such as addition, subtraction, bit shift and table look-up. This frees up any available multipliers in the device for use in more complex tasks.

The Lattice CORDIC IP core is configurable and several functions can be implemented in the IP core: rotation, translation, sin and cos, and arctan. Two architecture configurations are available for the arithmetic unit: parallel (with single cycle data throughput) and word-serial (with multiple-cycle throughput). The input data, output data widths and iterative number are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for rounding.

Block Viterbi Decoder

Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the original sequence. In a digital transmit-receive system the digital data stream (e.g., voice, image or any packetized data) is encoded, modulated and transmitted through a wired or wireless channel. The data received from the channel at the receiver side is first demodulated and then decoded using the Viterbi decoder. The decoded output is equivalent to the transmitted digital data stream.

The Lattice Block Viterbi Decoder IP core is a parameterizable Viterbi Decoder for decoding different combinations of convolutionally encoded sequences. The decoder supports various code rates, constraint lengths and generator polynomials. It also allows soft-decision decoding and is capable of decoding punctured codes. The core can operate in continuous or block modes, whichever is required by the channel. Either Tail Biting or Zero Flushing convolutional codes can be decoded in the block mode. All the configurable parameters, including operation mode, generator polynomials, punctured block size and puncture pattern can be defined by the user to suit the needs of their application.  The code rate and puncture pattern can also be changed dynamically through input ports during decoder operation. The Lattice Block Viterbi Decoder IP core is compatible with many networking and wireless standards that use different methods of convolutional encoding at the encoder.

Block Convolutional Encoder

Convolutional encoding is a process of adding redundancy to a signal stream to provide error correction capability. In a digital communication system the digital data stream (such as voice, image or any packetized data) is first convolutionally encoded, then modulated and finally transmitted through a channel.

The Lattice Block Convolutional Encoder IP core is a parameterizable core for convolutional encoding of continuous or burst input data streams. The core allows different code rates and constraint lengths and supports puncturing. It can operate in continuous or block mode, whichever is required by the channel. In block mode, either Zero Flushing or Tail Biting codes can be generated. All the configurable parameters, including operation mode, termination mode, generator polynomials, code rate, and puncture pattern, can be defined by the user to suit the needs of the application. The code rate and the puncture pattern can also be varied through the input ports dynamically, providing further flexibility for the IP usage. Lattice’s Block Convolutional Encoder IP core is compatible with many networking and wireless standards that use convolutional encoding.

Dynamic Block Reed-Solomon Decoder

Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy in the data before it is transmitted to allow error correction at the receiver. The redundant data (check symbols) are transmitted with the original data to the receiver. A Reed-Solomon decoder is used in the receiver to correct any transmission errors. This type of error correction is widely used in data communications applications such as Digital Video Broadcasting (DVB) and Optical Carriers (i.e. OC-192).

The Lattice Dynamic Block Reed-Solomon Decoder IP core is compliant with several industry standards including the recent IEEE 802.16-2004 and can be custom configured to support other non-standard applications as well. The Decoder supports a wide range of symbol widths and allows the user to define the field polynomial, generator polynomial and several other parameters. Newer standards like IEEE 802.16-2004 require the use of Reed-Solomon codes with dynamically varying block sizes. The Lattice Dynamic Block Reed-Solomon Decoder IP core provides an ideal solution that meets the needs of today’s forward error correction world. This IP core allows the block size and number of check symbols to be varied dynamically through input ports. 

Dynamic Block Reed-Solomon Encoder

The Lattice Dynamic Block Reed-Solomon Encoder IP core can be used for forward error correction in many terrestrial communication, space communication, data storage and data retrieval systems. The encoder is compliant with several industrial standards including the recent IEEE 802.16-2004. The Reed-Solomon Encoder IP core provides a customizable solution allowing forward error correction in other non-standard applications as well. The encoder supports both a fixed, as well as a variable number of total symbols (block) and check symbols. In the variable configurations, either the block size or both the block size and check symbols can be dynamically varied through ports. The core allows dynamic output check symbols puncturing in the fixed check symbols configurations.

FFT Compiler

The Lattice FFT Compiler IP core offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384. This IP core can be configured to perform forward FFT, inverse FFT (IFFT) or port-selectable forward/inverse FFT. The FFT compiler offers two choices of implementation: high performance (streaming I/O) and low resource (burst I/O). In the high-performance implementation, the FFT IP core can perform real-time computations with continuous data streaming in and out at clock rate. There can also be arbitrary gaps between data blocks allowing discontinuous data blocks. The low-resource implementation can be used when it is required to use lesser slices (logic unit of Lattice FPGA devices) and EBR (Embedded Block RAM) resources or if the device is too small to accommodate the high performance version. To account for the data growth in fine register length implementations, the FFT compiler allows one of three fixed scaling or dynamic scaling after each radix-2 stage of the FFT computation. The low-resource version also supports block floating point arithmetic that provides an increased dynamic range for intermediate computations. The FFT compiler also allows the number of FFT points to be varied dynamically through a port.

To Learn More

See the IP Support for the Recently-Released LatticeECP3 Family article in the May 2009 edition of LatticeNEWS for information on other released IP cores for the LatticeECP3 family.