June 2007

New LatticeXP2 FPGA Family Doubles Density and Cuts Cost

New generation provides double the density, higher performance, lower power and enhanced non-volatility while cutting price per function in half.

On May 29th, Lattice announced the availability of its third generation non-volatile FPGAs, the LatticeXP2 family. With enhanced capabilities, the LatticeXP2 family doubles maximum logic capacity to 40K Look-Up Tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%. Power consumption has also been optimized on the 1.2V process technology, reducing static power usage by 33%. Designed using the industry's most advanced non-volatile FPGA technology, a 90nm embedded Flash process co-developed with Lattice's foundry partner Fujitsu, the LatticeXP2 devices use an architecture referred to as flexiFLASH that provides the “instant-on” and reduced footprint benefits of earlier Lattice non-volatile devices, while also enhancing design security, RAM back-up and live update capabilities.

Architecture

The LatticeXP2 family consists of five members, with capacities from 5K to 40K 4-input Look Up Tables (LUTs).  Embedded block memory provides up to 885Kbits in 18Kbit dual port blocks. For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 8 sysDSP blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices have up to four Phase Locked Loops (PLLs) that allow designers to align and synthesize clocks as required in their designs.

LatticeXP2 Block Diagram

I/O capacities for the family range from 86 to 540 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps. LatticeXP2 devices are available in a number of space saving Chip Scale Ball Grid Array (csBGA) packages, thin as well as standard Fine Pitch Ball Grid Array (ftBGA and fpBGA) packages and popular TQFP and PQFP options.

flexiFLASH Architecture

Flash memory blocks are embedded within LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFLASH architecture. At power-up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device. This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1ms, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately on-board or stacked in the same package. This instant-on capability is critical for many system functions such as:

• Power up sequencing
• Address decoding
• Reset logic

flexiFLASH architecture provides a single chip solutioon, instant-on,
FlashBAK EBR, TAG memory and design security.

By keeping the configuration bitstream on-chip, the LatticeXP2 devices are also inherently more secure than alternative multiple device or multi-chip module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.

128-Bit AES bitstream encryption

The devices support up to 885Kbits of FlashBAK memory. This exclusive capability allows Embedded Block RAMs to be initialized at power up from Flash memory. During device operation, designers can also choose to write updated data from the block RAM back into the Flash memory. This provides a method to store data such as Power On Self Test (POST), microprocessor code and calibration data. An additional 0.6 to 3.3kbits of Flash memory is provided in the form of Serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.

FlashBAK technology allows storage of multiple data types.

A Comprehensive Solution for Field Updates

Increasingly, electronic equipment is designed to support field updates and bug fixes. It is critical that these updates are done reliably, securely and, in many cases, without interrupting equipment operation. The LatticeXP2 devices address these three requirements. To protect against incomplete new configuration downloads due to communication or system failures during field updates, a “golden configuration” can be stored in an optional external SPI boot memory and the LatticeXP2 device can boot automatically from this configuration if bitstream errors are detected. An on-chip, user-defined 128-bit AES decryption key and associated circuitry allows programming data to be encrypted and securely sent to the device remotely, preventing program intercept and piracy. The devices also support TransFR (Transparent Field Reconfiguration) technology that allows new configurations to be loaded into the LatticeXP2 device while the I/O states are precisely controlled, allowing new configurations to be applied while the overall equipment continues to operate.

Availability

Samples of the first member of the LatticeXP2 family, the 17K LUT LatticeXP2-17, in 208PQFP, 256ftBGA and 484fpBGA packages are available now and supported with the Lattice ispLEVER design tools and ispLeverCORE IP. Lattice plans to bring the entire device family to market during 2007.