June 2007

Reveal: A New Solution to an Old Problem 

A push-button flow for in-system logic debug now available.

FPGA designers have long faced the task of verifying functional correctness of their designs. Simulation plays a large part of this task, but checking the functionality of the device in the system is often required. If an issue is found, finding and fixing it can be a daunting task. The new Reveal software included in ispLEVER 7.0 is a next generation FPGA on-chip debug tool. It consists of the Reveal Inserter and the Reveal Analyzer.

The Reveal Inserter enables you to select which design signals to use for debug tracing or triggering, then generates debug logic on the basis of these signals and their usage. After generating the required logic, it generates a modified design with the necessary debug connections and links it to the signals. The Reveal Inserter supports VHDL, Verilog, and EDIF flows for debug insertion. Reveal also supports multiple debug cores (needed for multi-clock design debug), trigger outputs, and simultaneous trigger enables. Once the design has been modified for debug, it is mapped, placed, and routed with the normal design flow in ispLEVER. The Reveal Logic Analyzer helps you debug your FPGA circuitry by allowing the dynamic setting of all trigger conditions and the ability to view captured data in a waveform view or export the data as VCD or an ASCII file.

Easier Design Flow

Inserting or removing debug with Reveal is easier than ever before. To insert debug, the Reveal Inserter shows all the available signals in the design, allows for trace and triggering signals to be assigned, and then all debug insertion is handled with a single button press. The Reveal Inserter is also integrated with Project Navigator. If the original design is altered, debug will be automatically re-inserted during build database. To remove debug from the design, simply remove the Reveal “rvl” file from the Project Navigator source file list.

Reveal Design Flow

Advanced Triggering

The Reveal software has some important similarities and differences compared to external logic analyzers. An external logic analyzer typically offers up to a few dozen signals or channels and megabits worth of capture data depth. Internal logic analyzers have different constraints. An internal logic analyzer can offer thousands of signal connections, since there is no pin overhead on connecting to the signal. But the resources inside an FPGA force a limitation on the amount of data that can be captured, typically constrained to several thousand bits. This difference drives different requirements. An internal logic analyzer requires the ability to accurately pinpoint the desired event in order to capture a smaller amount of data around that precise event. The capabilities in the Reveal software are designed specifically for the triggering requirements for an internal logic analyzer.

Reveal Inserter and Analyzer Graphical User Interface

Triggering in Reveal is based on the trigger unit and the trigger expression. A trigger unit is used to compare signals to a value, and a trigger expression is used to combine trigger units to form a trigger. Some of Reveal’s triggering features are static and some are dynamic. Static features can only be changed in the Reveal Inserter and require the design to be re-implemented. All dynamic features, however, can be changed at debug time with no design change needed. All trigger unit comparison operators, comparison values, and trigger expressions are dynamic.

The trigger unit is used to compare a number of input signals to a value. Each trigger unit can be up to 256 signals wide and up to 16 trigger units can be supported in a single debug core. A wide range of operators are available including a serial compare function.

Trigger expressions are combinations of trigger units. Trigger units can be combined in combinatorial, sequential, and mixed combinatorial and sequential patterns. A trigger expression can be dynamically changed at any time. Each debug core supports up to 16 trigger expressions that can be dynamically enabled or disabled in the Reveal Logic Analyzer software. The trigger expression supports AND, OR, XOR, NOT, THEN, and parenthesis for setting precedence. Each part of a trigger expression, called a sequence, can also be required to be valid a number of times before continuing to the next sequence in the trigger expression by using a count (#) notation. These dynamic trigger expressions offer advanced capabilities not previously available in any logic analyzer tool.

Summary

Reveal is currently supported for  LatticeECP/EC, LatticeXP, LatticeECP2/M, LatticeSC/M, and LatticeXP2 devices. Reveal offers a much easier design flow integrated with Project Navigator for managing hardware debug, simple one-button debug insertion, and advanced triggering features.