June 2007

New PCI Express x4 Endpoint IP Core Solution

New core is compliant with PCI Express version 1.1 specification, enabling interoperability with the latest PCI Express-based systems.

With the introduction of the x4 Endpoint IP (Intellectual Property) Core solution, Lattice continues to expand its suite of offerings for companies needing high-performance PCI Express solutions in low-cost FPGA devices. Like the x1 Endpoint IP Core introduced last year, this core takes advantage of several value-oriented attributes in the LatticeECP2M device family - low-cost FPGA fabric, small footprint packages and cost-optimized SERDES channels all of which fit the requirements of many cost and form factor-sensitive performance-oriented applications.

Architecture Extensible to Datapath-Intensive and Bridging Applications

While the x1 Endpoint IP Core provides a performance upgrade for many PCI-based applications, especially control applications, the multiple lanes of the PCI Express x4 IP Core deliver more horsepower for a number of datapath-intensive applications such as communications, storage, medical, and video. In such applications, the new core may even be used as a bridge to other high-speed protocols such as Gigabit Ethernet, S-ATA, Serial RapidIO, or HyperTransport.

The PCI Express x4 IP Core implements the transaction, data link, and most of the physical layer (PHY) in soft IP. The remainder of the PHY is implemented in the LatticeECP2M SERDES/Physical Coding Sublayer (PCS). The architecture of the core leverages the previous x1 IP core, but adds a channel alignment block in the PHY layer that controls the alignment of the four PCI Express lanes.

Lattice PCI Express x4 IP Core Protocol Support

Small Footprint and Cost

The LatticeECP2M PCI Express x4 endpoint core requires just over 12,000 FPGA look-up tables (LUTs) and can easily be implemented in the smallest member of the LatticeECP2M family, the LatticeECP2M-20. As a result, the small size of the core enables implementation of a reasonable amount of value-added functionality within the LatticeECP2M device. When combined with the 20 x 20 mm 144-pin TQFP package available for LatticeECP2M-20, Lattice delivers a very small, high-performance PCI Express solution that is ideal for datapath-intensive applications, while offering programmability and cost that is advantageous versus PCI Express standard products or ASSPs.

Risk-Free Evaluation and Interoperability

Like all of Lattices PCI Express solutions, the x4 IP Core is available with an evaluation board, as well as free demos, and drivers, which makes evaluating the core a risk-free process. Furthermore, the core is also compliant with PCI-SIGs latest PCI Express version 1.1 specifications, enabling interoperability with a large base of existing hardware.

Design Tool Support

The latest version of Lattice's ispLEVER design tool suite supports the new x4 Core. It is also supported by an easy-to-use demo package that is optimized for the LatticeECP2M PCI Express x4 Evaluation Board. Like all IPexpress-based cores from Lattice, the x4 Core is available for free evaluation - just download from the Lattice web site, install, and configure all at no charge.