| Title |
Description |
Web |
Print |
Order # |
| General Information |
| Package Selector Card |
Features actual size package photos and specification tables for the most popular Lattice device families. |
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I0183E |
| LatticeXP2 FPGA Family Product Brief |
Discusses the new low-cost non-volatile LatticeXP2 FPGA family. |
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I0192 |
| LatticeMico32 Product Brief |
Discusses the soft core 32-bit microprocessor optimized for Lattice programmable devices. |
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I0186 |
| ispLEVER Design Tools Brochure |
Overview of Lattice's complete design environment for tasks including project management, IP integration, design planning, place and route, in-system logic analysis, and more. |
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| ispLEVER Maintenance Program Brochure |
Explains the benefits of keeping software maintenance active. |
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| ispLEVER Upgrade Brochure |
Describes the benefits of upgrading from the downloadable ispLEVER-Starter tools to the full ispLEVER software suite. |
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| LatticeXP2 Standard Evaluation Board User's Manual |
Guidelines for operation of the LatticeXP2 Standard Evaluation Board. |
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| LatticeECP2 Advanced Evaluation Board User's Guide |
Guidelines for operation of the LatticeECP2 Advanced Evaluation Board. |
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| ispPAC-POWR607 Evaluation Board User's Guide |
Guidelines for operation of the ispPAC-POWR607 Evaluation Board. |
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| LatticeECP2M PCI Express x4 Evaluation Board User's Guide |
Guidelines for operation of the LatticeECP2M PCI Express x4 Evaluation Board. |
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| LatticeECP2M SERDES Evaluation Board User's Guide |
Guidelines for operation of the LatticeECP2M SERDES Evaluation Board. |
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| LatticeSC PCI Express x1 Evaluation Board User's Guide |
Guidelines for operation of the LatticeSC™ PCI Express x1 Evaluation Board. |
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| Data Sheets and Handbooks |
| LatticeXP2 Family Data Sheet |
Full specifications for Lattice's new low-cost non-volatile LatticeXP2 FPGA family. |
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| LatticeXP2 Family Handbook |
Complete LatticeXP2 Family Data Sheet plus detailed technical notes on using the key features of this FPGA family. |
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| LatticeECP2/M Family Data Sheet |
Full specifications for Lattice's low cost, high performance FPGA family. |
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| LatticeECP2/M Family Handbook |
Complete LatticeECP2/M Family Data Sheet plus detailed technical notes on using the key features of this FPGA family. |
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| LatticeSC Family Data Sheet |
Full specifications for the LatticeSC (System Chip) family of FPGAs. |
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| LatticeSC Family flexiPCS Data Sheet |
Full specifications for the embedded multiprotocol Physical Coding Sublayer in the LatticeSC FPGA. |
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| MachXO Family Data Sheet |
Full specifications for the MachXO, low-cost, non-volatile, infinitely reconfigurable Crossover CPLD family. |
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| MachXO Family Handbook |
Complete MachXO Family Data Sheet plus detailed technical notes on using the key features of this device family. |
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| LA-MachXO Automotive Family Data Sheet |
Full specifications for Lattice's low-cost, non-volatile, infinitely configurable crossover PLD now available in automotive temperature ranges. |
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ispPAC-POWR607
Data Sheet |
Full specifications for Lattice's In-System Programmable power supply supervisor, reset generator and watchdog timer. |
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ispPAC-POWR1220AT8
Data Sheet |
Full specifications for Lattice's In-System Programmable power supply monitoring, sequencing and margining controller. |
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ispPAC-POWR6AT6
Data Sheet |
Full specifications for Lattice's power-supply monitoring and trimming/margining controller. |
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ispPAC-POWR1014/A
Data Sheet |
Full specifications for Lattice's In-System programmable power supply supervisor, reset generator and sequencing controller. |
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ispClock5300S
Family Data Sheet |
Full specifications for Lattice's single ended In-System Programmable, zero delay universal fanout buffer. |
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| Technical Notes |
| LatticeXP2 sysIO Usage Guide |
The LatticeXP2™ sysIO buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how they can be implemented using ispLEVER design software. |
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| LatticeXP2 sysCLOCK PLL Design and Usage Guide |
Describes the clock resources available in the LatticeXP2 device architecture, including primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, clock dividers and more. |
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| LatticeXP2 Memory Usage Guide |
A guide for integrating the User TAG, EBR- (Embedded Block RAM) and PFU-based memories in the LatticeXP2 family using the ispLEVER design tool.
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| LatticeXP2 High-Speed I/O Interface |
Details the use of LatticeXP2 devices to implement both a high-speed generic DDR interface as well as DDR and DDR2 memory interfaces.
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| Power Estimation and Management for LatticeXP2 Devices |
Describes how to use the ispLEVER Power Calculator tool to calculate the power consumption of the LatticeXP2 devices. General guidelines to reduce power consumption are also included. |
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| LatticeXP2 sysDSP Usage Guide |
Discusses how to access the features of the LatticeXP2™ sysDSP™ (Digital Signal Processing) Block. Designs targeting the sysDSP Block can offer significant improvement over traditional LUT-based implementations. |
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| LatticeXP2 sysCONFIG Usage Guide |
This technical note covers all the configuration options available for the LatticeXP2, including Slave SPI, Master SPI and ispJTAG. |
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| LatticeXP2 Configuration Encryption and Security Usage Guide |
This document explains the encryption and security features of the LatticeXP2 and how to take advantage of them. |
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| LatticeXP2 Soft Error Detection (SED) Usage Guide |
Describes the LatticeXP2's hardware-based soft error detect (SED) which does not affect performance or heat dissipation of the device. |
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| LatticeXP2 Dual Boot Usage Guide |
Describes how to use external Flash memory with the LatticeXP2, allowing storage of alternate bitstream configurations. |
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| TN1143 - LatticeXP2 Hardware Checklist Technical Note |
Covers three critical hardware topics: (1) power supplies as they relate to the LatticeXP2 supply rails and how to connect them to the PCB and the associated system, (2) configuration and how to connect the configuration mode selection for proper power up configuration, and (3) device I/O interface and critical signals. |
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| LatticeECP2M PBRS SERDES Demo User's Guide |
This demo illustrates the SERDES/PCS abilities of the LatticeECP2M by embedding a simple pseudo-random pattern into an 8b10b encoded PCS payload, then looping back the payload, and checking it for correctness. |
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| LatticeECP2M High Speed Backplane Measurements |
Outlines two experiments that measure the SERDES backplane transmission performance thresholds of the LatticeECP2M products.
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| LatticeECP2/M Dual Boot Usage Guide |
Describes how to use external Flash memory with the LatticeECP2/M families, allowing storage of alternate bitstream configurations. |
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| LatticeECP2M High Speed Backplane Measurements |
This technical note outlines two experiments that measure the SERDES backplane transmission performance thresholds of the LatticeECP2M FPGA. |
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| Mixed-Language Simulation with Lattice IP Designs Using Active-HDL |
Explains how to perform mixed Verilog/VHDL language simulation for designs incorporating Lattice IP cores by using the Active-HDL simulation tools from Aldec. |
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| Mixed-Language Simulation with Lattice IP Designs Using ModelSim |
Explains how to perform mixed Verilog/VHDL language simulation for designs incorporating Lattice IP cores by using the ModelSim simulation tools from Mentor Graphics. |
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| Reference Designs |
| LatticeECP2/M 7:1 LVDS Video Interface |
Discusses the requirements for implementing a 7:1 LVDS interface and the advantages of using the LatticeECP2/M in such an interface. |
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| LMS Adaptive Filter |
Describes the Least Mean Square (LMS) algorithm that can be used to estimate a time varying signal.
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| Intellectual Property |
| LatticeECP2M PCI Express x4 Endpoint IP Core User's Guide |
Detailed user's guides for Lattice's latest IP core products.
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| Tri-Speed Ethernet Media Access Controller IP Core User's Guide |
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| LatticeMico32 IP Core User's Guide |
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| DDR SDRAM Controller - Pipelined IP Core User's Guide |
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| DDR2 SDRAM Controller - Pipelined IP Core User's Guide |
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| Cascaded Integrator-Comb (CIC) Filter IP Core User's Guide |
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| FFT Compiler IP Core User's Guide |
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| Numerically Controlled Oscillator IP CCore User's Guide |
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| Block Viterbi Decoder IP Core User's Guide |
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| Dynamic Block Reed-Solomon Decoder IP Core User's Guide |
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| Dynamic Block Reed-Solomon Encoder IP Core User's Guide |
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| IPUG18 - PCI IP Core User's Guide |
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New Account
June 2007