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LatticeNEWS June 2007

Contents

Lattice Listens

Questions:

 

What new capabilities does the LatticeXP2 device family offer?

LatticeXP2 is the industry’s first, truly integrated Flash-based FPGA that offers densities from 5K to 40K LUTs. The integrated Flash technology allows Lattice to continue technology migration from the LatticeXP FPGA family and offer features such as an instant-on, infinitely re-configurable, single-chip solution, and competitive density migration over similar packages. LatticeXP2 also adds capabilities such as sysDSP blocks, FlashBAK user Flash capability, Serial TAG memory, and security features such as encryption and OTP. These are features that only the single-chip Flash technology can offer and any other technology that claims to be a Flash-based FPGA is only an imitation of the “real thing”.


When using 16-bit gearing and word alignment, how can I determine where an 8-bit comma character will appear in the RX 16-bit LatticeSC FPGA/PCS interface data?

The 8-bit comma character will always occur in the same 8-bit word location in the 16-bit RX data, as long as the transmitter never sends back-to-back commas or sends commas that are an odd number of cycles apart. The logic will monitor the 8-bit words for the occurrence of the comma character. This applies to the Generic 8b10b, Fibre Channel, XAUI, PCI Express and Serial RapidIO modes of the LatticeSC SERDES/PCS configuration.


How can I correct the RX data of a LatticeSC SERDES interface if the 8-bit comma character is sent in the upper 8 bits of the 16-bit TX data but is shifted into the lower 8-bit word of the RX 16-bit data?

If the 16-bit boundary is identical to the TX data, then nothing needs to be corrected; the data is received as it was transmitted. If the 16-bit boundary is off by one 8-bit word, then the alignment needs to be corrected. For example, assume B4 is a K28.5 comma.

If the data transmitted is B0B1 B2B3 B4B5 B6B7 (where the even indexed bytes are the lower 8 bits of the 16-bit TX data) and the data received is the same, no correction is necessary. If the data transmitted is B0B1 B2B3 B4B5 B6B7 but the data received is B1B2 B3B4 B5B6, then the 16-bit boundary is off by one 8-bit word and the alignment should be corrected. To correct the alignment, a simple piece of code can be written to replace the current cycle's upper 8-bit word with the current cycle's lower 8-bit word and to replace the current cycle's lower 8-bit word with the previous cycle's upper word. The data received will then look like the data transmitted.


Does ispLEVER support mixed language, Verilog/VHDL simulation?

This question has become more important for designers who prefer a VHDL environment for simulation; the use of a single-kernel mixed-language simulator with Lattice FPGA device library support is required. EDA tools such as Active-HDL from Aldec provide this feature.

Lattice IP cores are distributed using an obfuscated Verilog RTL simulation model and an encrypted Verilog gate-level model. If the FPGA application is being developed in VHDL, the IP must be instantiated as a component, and then the entire FPGA application can be simulated as though the IP were a VHDL design. Once the core has been generated by IPexpress, a VHDL wrapper must be created for instantiating the obfuscated Verilog RTL simulation model. In Active-HDL, a designer creates an Entity/Architecture pair complete with the component declaration and component instantiation using the Block Diagram Editor Tool. This tool reads in the Verilog top-level module port list and creates a symbol. The designer then connects I/O ports and signals to the symbol. After selecting VHDL as the target language, the Entity/Architecture pair is push-button generated, and the component is instantiated within to create the VHDL wrapper. The newly created VHDL wrapper can then be instantiated in a VHDL testbench or in a top-level VHDL design. The design may now be compiled for simulation using vcom for the VHDL design units and vlog for the Verilog modules.


My design does not need power supply sequencing. Is there still a benefit to using Power Manager in my circuit?

Power Manager integrates some of the typical circuit board functions such as CPU reset generation, Voltage Supervision, watchdog timer and hot-swap/Soft Start in addition to power supply voltage sequencing. Even if your circuit board requires any two of the above four functions, it is likely to be less expensive to use a Power Manager device instead of your existing solution. In addition, the Power Manager also increases your circuit board reliability by monitoring all of the circuit board power supply rails with higher accuracy and reduces the number of components on the circuit board.