June 2007

LatticeSC/M FPGAs Deliver Industry’s Fastest Memory and HyperTransport I/O

1.6 Gbps HyperTransport, 667Mbps DDR2, 750Mbps QDR2+, 800Mbps RLDRAM II

Results announced after additional characterization of both Lattice IP and the LatticeSC and LatticeSCM devices in flip chip packages.

Memory Controllers Optimized With MACO

These memory speeds are as fast as any in the industry and rely on Lattice’s unique embedded design technology called MACO (Masked Array for Cost Optimization). Using embedded technology reduces the FPGA resources, both logic gates and power, needed to implement these controllers. In addition, these pre-engineered design functions enable users to reduce design cycles and thereby quicken their end-system time to market. MACO technology is available on the LatticeSCM family of devices (not included with the LatticeSC family).

HyperTransport is the Fastest in the Industry

The LatticeSC/M’s innovative Purespeed I/O can support HyperTransport interfaces operating as fast as 1600Mbps. This is twice as fast as competitors can claim for their leading architectures, even for their next generation devices. This significant improvement in speed is extremely attractive to users who plan to rely on FPGAs in application-specific co-processing subsystems for HyperTransport.

Multi-Bit LVDS I/O Reference Design Now Available

A new reference design called the Purespeed I/O Alignment Reference Design demonstrates the power of the LatticeSC/M’s patented Adaptive Input Logic block. AIL is designed to continuously monitor and dynamically adjust the clock/data relationship on a bit-by-bit basis. This ability is critical for users who want to build large, high-speed data pipes out of multiple smaller ones. In the demo, data is sent across mismatched trace lengths to introduce different amounts of skew. A word alignment block, together with AIL, is used to realign this skewed data bus.

The reference design is available at no charge by contacting your local Lattice sales representative.