June 2007

Lattice Launches LatticeECP2 and LatticeECP2M Security Series (S-Series)

LatticeECP2 family production release complete!

In order to provide increased design flexibility to its customers, Lattice has released a new series of devices, the S series (for Security), for both the LatticeECP2 and LatticeECP2M families, to support applications requiring bitstream encryption. The S-Series devices are pin-compatible and provide the same footprint as the standard series of the LatticeECP2/M devices. All members of the LatticeECP2 family, including the S-Series devices are now fully released to production and shipping in volume. In addition, a new package option for the LatticeECP2M family, the 1152-ball Fine Pitch BGA (fpBGA) package for the 70K LUT and 100K LUT devices is now available.

The LatticeECP2/M devices have been optimized to deliver the features and cost structure required by designers for high-volume applications. Key points include:

• Optimized Logic and Routing Fabric: The logic block and routing have been optimized to tailor features such as distributed memory (provided on 12.5% of LUTs) and registers (provided on 75% of LUTs) to the typical application set. The resulting logic fabric allows easy high performance logic implementation.
• Pre-engineered 840Mbps Parallel I/O: The rise of DDR memories and other similar standards leaves many designers grappling with the challenge of implementing high performance parallel I/O interfaces within FPGAs. To meet this need, designers have historically had to utilize high cost FPGA solutions. The LatticeECP2 devices provide DDR mux/de-mux, precision delay and gearbox logic elements. These can be combined to implement pre-engineered DDR2 (533Mbps) and other source synchronous interfaces operating at up to 840Mbps for applications such as SPI4.2 and ADC/DAC interfaces.
• Full Featured sysDSP Blocks: To support low cost DSP applications, the LatticeECP2 devices embed sysDSP blocks capable of implementing multiply, accumulate, summation and pipelining functions. The devices can implement DSP functions up to 28,600 Million Multiply Accumulates per second (MMACs) at prices below $0.001 per MMAC.
• Easy Field Logic Updates: In order to accommodate bug fixes, respond to standard changes and support the addition of new features and services, an increasing number of FPGA designs require FPGA logic updates in the field. The LatticeECP2 provides dual-boot support and Transparent Field Reconfiguration (TransFR) I/O to simplify field updates. The devices also support the storage of two or more configurations in industry standard Serial Peripheral Interface (SPI) PROMs. TransFR I/O capability allows designers to precisely control I/O states while a new configuration is loaded into the FPGA, a significant improvement over the more conventional practice of tri-stating I/Os during reconfiguration.
• Bitstream Encryption for Enhanced Design Security: To address increasing design piracy concerns, the LatticeECP2/M S-Series devices have on-chip, non-volatile key storage and decryption circuitry to allow the decryption of 128-bit AES encrypted bitstreams based on a unique user key. This brings the concept of bitstream encryption to low-cost SRAM FPGA products for the first time, again reducing the need for higher cost FPGAs in many designs.