June 2007

SPI4.2 to XAUI/HiGig™/HiGig+™ Bridging Solutions with LatticeSCM FPGAs

Lattice supports the latest 10G communications protocols with dedicated MACO blocks (embedded ASIC) included with the LatticeSCM family.

New 10 Gigabit Ethernet Service Cards are being implemented to include new features. These cards are found in Metro Switches, Edge and Core Routers, Ethernet Backbone Switches, Aggregation Routers, Access Nodes and more. The key functional silicon nodes on these cards are Ethernet Switches.

HiGig™ and HiGig+™

A number of the implementations use the Broadcom® StrataXGS® family for the Ethernet Switch. For the StrataXGS® family, Broadcom® has implemented a proprietary protocol called HiGig™. The HiGig™ protocol supports various switching functions like Quality-of-Service (QoS), link aggregation, and others. The physical signaling across the interface is XAUI, four differential pairs for receive and transmit (SERDES), each operating at 3.125 Gbps. HiGig+™ is a higher rate version of HiGig™.

A block diagram for this bridge is shown below. The NPUs (e.g., EZChip's NP-2/NP-3, others),  typically have a SPI4.2 interface to link to the fabric side. Most of the Ethernet switches have a XAUI link. Therefore, a bridge is required to go from the SPI4.2 interface on the NPU to the XAUI/HiGig™/HiGig+™ interface on the Ethernet Switch.

SPI4.2 to XAUI/HiGig™ System Block Diagram

Features

• Supports full-duplex bridging between NPUs (through SPI4.2) and Ethernet Switches (XAUI/HiGig™/HiGig+™).
• Support HiGig+™ datarates on the SERDES.
• Supports SPI4.2 datarates up to 1 Gbps per pin (500 MHz clock).
• Support for up to 256 channels on SPI4.2 side.
• Supports flow control in both directions.
• 32KByte shared buffer each in Ingress and Egress directions.
• Supports minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized Network Processor applications marking of all errored packets received before transmitting.
• Controllability and observability through Processor interface.
• Supports statistics collection from the MAC. 

Advantages

• The LatticeSCM SPI4.2 to XAUI/HiGig™ Bridge is the industry’s lowest power and smallest footprint solution.
• Industry’s lowest power SPI4.2, implemented in MACO.
• A single configuration of the bridge is implemented in the LatticeSCM15 in the 256-fpBGA package (17x17mm), the smallest footprint solution available in the industry. 
• High performance, low power SERDES that can support HiGig+™ rate (Lattice SERDES are rated up to 3.8 Gbps). 
• Lattice developed IP solution, Lattice supported. Competitor’s solutions are from third-party IP vendors and involve hefty NREs.
• Multiple users already designing with the Lattice solution.

The Lattice SPI4.2 to XAUI/HiGig™ IP core will be released in June 2007. For further information on Lattice bridging solutions, please contact your local Lattice sales representative.

Broadcom®, HiGig™, HiGig+™, and StrataXGS® are trademarks of Broadcom Corporation and/or its affiliates in the United States, EU and/or certain other countries.