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LatticeNEWS June 2007

Contents

On-Screen Display Functions Enhance 7:1 LVDS Video Interface Reference Design

Expanded video functionality plus simplified implementation, reduced component count and system cost.

Offering additional support for video customers, Lattice has recently enhanced its LatticeECP2/M 7:1 LVDS Video Interface Reference Design with additional Intellectual Property to include Color Space Converters, Hue, Saturation, Brightness, Contrast and On-Screen Display functionality. An instance of the LatticeMico8 8-bit RISC CPU was also added as part of the On-Screen Display generator and for control on the on-board demonstration mode.

 

LVDS Color Balance Adjustments

The LatticeECP2/M FPGA families are well suited for
high-speed LVDS video applications and on-screen display functionality

 

The 7:1 LVDS Video Interface reference design illustrates how to use the pre-engineered I/O components within the low cost LatticeECP2/M FPGA families to implement the “7:1” source synchronous LVDS (Low Voltage Differential Signaling) interfaces commonly found in display applications. By integrating the 7:1 LVDS interfaces within its FPGAs, Lattice enables designers to reduce component count and system cost. This reference design illustrates how the high performance I/O capabilities of the LatticeECP2/M FPGAs can be used in display applications for the consumer, automotive and industrial instrumentation markets.

7:1 LVDS Interfaces

Display applications require the transfer of large amounts of data across multiple boards within a system. Often this transfer is implemented with high-speed LVDS interfaces that typically consist of three or four data lines and a clock. Seven data bits are transmitted for every clock period, and commercially available parts support clock rates of 105MHz and beyond, which translates into data rates of 749Mbps and higher.

There are three key challenges associated with implementing high-speed 7:1 LVDS interfaces within FPGAs:

  • High-speed LVDS buffers are required.
  • High-speed data streams need to be serialized and de-serialized.
  • Skew between data and clock bits must be managed in order to avoid eroding the timing margin.

Pre-engineered I/O Components Simplify Implementation

The display interface reference design takes advantage of the LatticeECP2/M devices’ pre-engineered components that simplify the implementation of 7:1 LVDS interfaces. The LatticeECP2/M FPGAs contain integrated LVDS receivers and drivers capable of 840 Mbps performance. Built-in gearbox logic allows a 4X reduction in data rate before the data enters the Look-up Tables (LUTs) at the core of the FPGA. Built-in edge clocks minimize the skew between data and clocks. These pre-engineered components allow 7:1 LVDS interfaces to be easily constructed, without the need for manual placement of LUT logic within the devices. The components also provide more timing margin, which permits a more robust and manufacturable design.

Evaluation Kit

To facilitate testing and evaluation of the LatticeECP2/M devices in display applications, Lattice offers a set of daughter cards for use with its LatticeECP2 evaluation board. These daughter cards allow Digital DVI image data from a source device, such as a PC, to be passed through other vendors’ devices and is ultimately converted into 7:1 LVDS format before being passed though a cable to the LatticeECP2 board. The LatticeECP2 device receiving the data then performs image manipulations and passes the data off the board, again using a 7:1 LVDS format. A final board converts the 7:1 LVDS data into DVI format, which is then passed to a display.

Ordering Information

The VHDL and Verilog sources for the high-speed LVDS display interface reference design are available for free download from the Lattice website.