July 2011Two trends are driving up the processing requirements in the rapidly growing market for security and surveillance cameras: the introduction of megapixel sensors and High Dynamic Range (HDR). Multi-megapixels are required to capture more detail per frame, while HDR processing is required for image details to be equally visible in bright and dark areas of the frame, without the details being washed out due to too much light or invisible due to too little light. Together, these two trends have driven up the number of pixels that need to be processed per image frame.
A leading provider of urban surveillance cameras was faced with the need to manufacture HDR security cameras for the domestic and international markets at an aggressive cost target. The manufacturer examined traditional DSP-based options and concluded that these solutions were too expensive in terms of both cost and power budget. Also, the image quality and HDR performance after processing needed to be “of a very high order.”
After evaluating the Lattice HDR-60 Video Camera Development Kit and the associated Image Signal Processing (ISP) IP from Lattice partner Helion Vision, the manufacturer decided to design the high-end HDR camera using the LatticeECP3-70 FPGA, running the Helion ISP IP and Lattice Multi-Rate Serial Digital Interface (SDI) Physical Layer IP core.
HDR-60 Base Board with NanoVesta Head Board
The manufacturer selected the LatticeECP3 FPGA because it is supported by world-class ISP IP with a very small footprint and Lattice Multi-Rate SDI Physical Layer IP. In addition, use of the LatticeECP3 FPGA resulted in a bill-of-materials cost for the image processing electronics that was almost half that of a traditional DSP solution. The LatticeECP3 solution also consumed significantly less power and provided HDR performance that enabled the manufacturer to, in their words, “offer our customers high quality, truly differentiated HD cameras with HDR at very low system cost." The manufacturer also stated that the HDR-60 Video Camera Development Kit enabled them to accelerate their design cycle, resulting in a significant time-to-market advantage. In addition, the Helion ISP IP cores are available as modular IP blocks with various image processing functions from which the manufacturer could pick and choose, whereas competitiors provided only a monolithic image processing block.
Example of Helion IONOS Image Signal Processing Pipeline
The Lattice HDR-60 Video Camera Development Kit is a fully functional camera that enables designers to demonstrate the features of the Helion ISP IP running on a LatticeECP3 FPGA. The IP is capable of supporting full HDR 1080p at 60 frames per second. The kit is equipped with an Aptina 720p sensor.
For more information about the HDR-60 Video Camera Development Kit or the Multi-Rate Serial Digital Interface (SDI) Physical Layer IP core, visit the Lattice website.
© Lattice Semiconductor Corporation 2012
