July 2010

Full HD HDR Color Pipe for Video Security and Surveillance Applications

Innovative streaming high dynamic range IP utilizes FPGA fabric, DSP multipliers and embedded block RAM to provide 1080p60 video image signal processing without the need for an external frame buffer.

Lattice and Helion GmbH have released Intellectual Property (IP) cores for the video security and surveillance camera market. Helion has demonstrated its IONOS video pipeline IP and Vesta development platform on the LatticeECP3, LatticeECP2M and LatticeXP2 FPGA families. The Helion Vesta development platform is a completely self-contained platform that enables the development and realization of image pipelines for camera systems, especially in tight form-factor video security applications such as network IP and dome cameras.

Vesta Development Platform

The Helion Vesta Development Platform is a modular technology platform that combines a video processing baseboard, an image sensor and a Lattice FPGA capable of supporting a range of Helion IONOS video pipelines.

• 1080p60 performance supporting full HD at 60 frames per second
• Supports up to 12MP sensors – Offers seamless upgrade path and protects investment
• Low system cost and extremely low latency – 1080p60 streaming data path through the FPGA with no external frame buffer required
• Industry’s fastest auto exposure – Executes in three frames; no visible display bloom or blackout; quick response to fast changing light
• 120dB scene dynamic range – Maximum details under difficult lighting conditions, in both dark and light areas in a single image
• 192dB (32-bit) system dynamic range – Exceeds the 150dB automotive manufacturer-specified requirements
• Wishbone-compatible IP
• Comprehensive IP suite enabling end-to-end ISP (Image Signal Processing) solutions

Comprehensive IP Suite for End-to-End ISP Solutions

Helion offers a comprehensive selection of video pipelines, ranging from basic to advanced monochrome and color pipelines, to high resolution advanced High Dynamic Range Imaging (HDRI) color pipelines. Depending on the pipeline selected, it will consist of a number of individual video processing IP cores, such as defective pixel correction, logic-efficient 3x3 De-Bayering, high quality 5x5 De-Bayering, color-correction matrix, gamma correction, auto-exposure, auto-white balance and more. These cores support Lattice FPGAs, and are all compatible and simply connected with the Wishbone bus.

IONOS Imaging Pipeline Example

IP cores from Helion are available pre-configured as a complete working HDR pipeline, not simply as building blocks that the user needs to stitch together, offering quicker time-to-market and proven interconnect without the trial and error of do-it-yourself IP blocks.

To Learn More

For more information about security and surveillance solutions, please visit the Lattice web site.