July 2010

Lattice Diamond Design Software Heralds New Era for Low Power, Cost Sensitive FPGA Applications

New generation design tools are essential as FPGAs move to high volume applications.

Lattice has announced version 1.0 of its Lattice Diamond FPGA design software, the new flagship design environment for Lattice FPGA products. Lattice Diamond software provides a complete set of powerful tools, efficient design flows, and a modern user interface that enable designers to more quickly target low power, cost sensitive FPGA applications. Video demonstrations of the Lattice Diamond design software can be viewed on the Lattice web site.

Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. This combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.

 

Complete Design Environment

Diamond includes a complete set of tools covering all aspects of FPGA design.

• Design Entry
• Synthesis
• Implementation
• Power & Timing Analysis
• On-chip Debug Hardware Analysis
• Simulation
• Programming

 

Key Features

Design Exploration Made Easy

Projects / Implementations / Strategies

Diamond allows more robust projects and offers new capabilities for improved design exploration. Key features include:

• Mixing of Verilog, VHDL, EDIF, and schematic sources
• Implementations allow multiple versions of a design within a single project for easy design exploration
• Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
• Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
• Use Run Manager view for parallel processing of multiple implementations to explore design alternatives for the best results

 

 

HDL Code Checking

Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability.

Ease of Use Throughout

User Interface for a New Generation of Tools

The Diamond user interface combines leading-edge features and customization while offering better ease of use. All the tools in Diamond open in “Views” integrated into a common Diamond user interface. Once the operation for a single tool is learned, this knowledge can be applied to other tools.

Key elements of the Diamond user interface include:

• Common menu and button locations for all views
• Three user interface sections for tools, projects, and output
• Start Page – Open projects, import ispLEVER projects, online help, software updates
• Report View – Centralized location for all reports from implementation tools

Speeding Common Functions

• ECO Editor provides quick access to commonly-used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization.
• Programmer allows fast reprogramming of FPGAs once the hardware configuration has been set up with ispVM.

Improved Design Flow

Fast, Easy Timing Analysis

Timing Analysis view offers an easy-to-use graphical environment for navigating timing information. A key benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report.

 

 

Easy Design Export to Simulators

Diamond provides easy export of designs to simulators through the new Simulation Wizard.

Scripting with Tcl

Diamond software adds new capabilities for scripting the design flow. Diamond-specific Tcl command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis.

 

Powerful Third-Party Tools

Synopsys^® Synplify Pro™ for Lattice Synthesis

• Automatically produce an RTL schematic of your design
• Cross-probe with RTL source code
• Mixed VHDL and Verilog synthesis support
• Compile points
• Automatic re-timing (balancing registers across combinatorial logic)
• Automatic gated-clock and generated-clock conversion for efficient implementation of RTL written for an ASIC into an FPGA

Aldec^® Active-HDL™ Simulation

• Mixed language simulation of VHDL and Verilog (Aldec Active-HDL Lattice Edition II only)
• Language Assistant
• Code Execution Tracing
• Advanced Breakpoint Management
• Memory Viewing

 

Availability and Pricing

The Lattice Diamond software is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either the Diamond free license or the Diamond subscription license.

The Diamond free license can be immediately generated upon request from the Lattice website and provides access to many popular Lattice devices such as the MachXO PLD family, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family at no cost. The Diamond free license also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.

The Diamond subscription license that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 FPGA devices. It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance. The Diamond subscription license enables both the new Diamond software and existing ispLEVER software from a single license. The Diamond subscription license price is $895 per year. All Lattice ispLEVER software users under active maintenance agreements will receive a Diamond subscription license for no charge that will expire one year from the Lattice Diamond 1.0 release date.

 

Choosing The Right Software Tool

The following matrix summarizes some of the more important features of the current Lattice FPGA and logic design software tools. For current Lattice FPGA devices, Lattice Diamond is the recommended design software. For Lattice CPLD devices, ispLEVER Classic is the required design software.

	Lattice Diamond (subscription license) Windows/Linux	Lattice Diamond (free license) Windows/Linux	ispLEVER Classic Windows
Lattice FPGA/CPLD Support
LatticeECP3
LatticeXP2
LatticeECP2M/S
LatticeECP2
LatticeECP2S
LatticeSC/M
MachXO
LatticeECP/EC
LatticeXP
ispXPGA
ORCA FPGA
ORCA FPSC
ispXPLD 5000MX
ispMACH 4000B/C/V/Z/ZE
ispMACH 5000VG
MACH 4A3 / 4A5
ispLSI2000/5000
ispGDX/2
ispGAL / GAL
Software Features
Design Exploration
Project Management
VHDL & Verilog Support
EDIF Support
Schematic Support
sysDSP Library for MATLAB/Simulink / ispLeverDSP
ABEL
IP and Module configuration			Module Only
Power Estimation & Calculation
Timing Analysis
Integrated HDL Analysis
Floorplanning
EPIC Device Editor			ORCA FPGA only
On-Chip Debug			ispXPGA only
TCL Scripting Dictionaries
3rd Party Software Included
Synplify PRO for Lattice - Synthesis from Synplicity
Synplify for Lattice - Synthesis from Synplicity
Active-HDL Lattice Edition - Simulation from Aldec	Windows Only
Active-HDL Lattice Web Edition - Simulation from Aldec		Windows Only
Operating Systems
Windows 7
Windows XP, Vista (32-bit)
Linux (Redhat Enterprise v4, v5; Novell SUSE Enterprise v10 SP1, 11)
Licensing & Updates
License Terms	1 Year Subscription	1 Year - Renewable	1 Year - Renewable
Node-Locked License
Floating License

Note: Lattice Diamond subscription license allows either Diamond or the previous ispLEVER software to be run. Aldec simulation for Windows floating license requires a USB ID Key (ALDEC-USBKEY). Both of these products are available via the Lattice on-line store.