July 2009
A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
|---|---|---|---|---|
| General Information | ||||
| MachXO Product Brief | Introduction to Lattice's low-cost, non-volatile, infinitely reconfigurable PLD. |  |
— | — |
| Package Selector Card | Features actual-size package photos and specification tables for the most popular Lattice device families. | |
|
I0183Q |
| RoHS Compliant Packaging Product Brief | Overview of Lattice's lead-free and halogen-free RoHS-compliant products. | |
— | — |
| Data Sheets & Handbooks | ||||
| MachXO Family Data Sheet | Full specifications for Lattice's low-cost, non-volatile, infinitely reconfigurable PLD. | |
— | — |
| MachXO Family Handbook | Complete MachXO Family Data Sheet plus detailed technical notes on using the key features of this device family. | |
— | — |
| Application Notes | ||||
| Using a Discrete Crystal as a PLD Clock Source | This new application note describes the generation of a clock signal using an inexpensive crystal circuit to minimize board costs rather than using more expensive, integrated oscillators. | |
— | — |
| Using Multiple Boundary Scan Port Linker (BSCAN2) | The Lattice Multiple Boundary Scan Port Linker (BSCAN2) reference design provides a flexible solution to the problems presented by the growing number of IEEE1149.1-capable devices in today's complex systems. BSCAN2 allows a system designer to isolate devices in a way that makes the most sense for the test objectives and types of devices used. This application note describes the usage and implementation of the BSCAN2 reference design. | |
— | — |
| IP Core User's Guides | ||||
| Tri-Rate SDI PHY Layer IP Core User's Guide | Detailed user's guide for the Tri-Rate Serial Digital Interface Physical Layer IP core. | |
— | — |
| CPRI IP Core User's Guide | Detailed user's guide for the CPRI IP core. | |
— | — |
© Lattice Semiconductor Corporation 2012
