|
Driven by an increasing need to minimize board space in telecom infrastructure, server, industrial and consumer applications, Lattice has introduced a new 0.8-mm pitch 256-ball Chip-Array BGA (caBGA) package for the popular MachXO PLD family. This provides designers with a broader range of package options for implementing cost-sensitive, board space constrained designs. Full story...
Service pack 2 for version 7.2 of the ispLEVER design tool suite is available now without charge for users with active design tool maintenance contracts. This update expands the breadth of the tool suite’s overall capabilities, and includes important updates for the mid-range LatticeECP3 and non-volatile LatticeXP2 FPGA families. Full story...
Lattice has recently released two transceiver-based IP cores to support the LatticeECP3 family. Full story...
Save money on your next board design by using the MachXO PLD to get a high-quality clock from a less-expensive source. Full story...
Hans Schwarz, a former Xilinx Vice President, joined the Lattice Board of Directors June 4. Full story...
|
July 2009
© Lattice Semiconductor Corporation 2012
