July 2008

Lattice Listens

Q: As power consumption becomes a more critical element in system design, how do I analyze FPGA power consumption when using Lattice products?  

A: The Power Calculator tool that comes with the ispLEVER design software is an excellent place to begin your analysis of Lattice FPGA power consumption. (Note: The same standalone Power Calculator is available for download from the Lattice website). The complex nature of advanced FPGA technology, coupled with intricate FPGA designs, requires that power be analyzed based on both user logic implementation and environmental considerations. With the Power Calculator tool, user logic implementation and environmental considerations are loaded from the Map, Place & Route software along with the user entry conditions.

Based on these inputs, the Power Calculator output provides a reasonable estimation of static and dynamic power for the user environment. The figure below is a summary screen shot of the Power Calculator tool.

Power Calculator Grahpical User Interface

In addition to the user's active power, FPGA power-up initialization power should also be considered. This ensures that the power budget for the system can accommodate both normal active power and device initialization power.

Tips for saving power include careful consideration in resistive loading of the I/O pins, thermal management of the FPGA in the system environment, and paying attention to the activities of the entire FPGA. FPGA densities are such that reducing logic activities when portions of the device are not being used can be considered as part of the overall power saving strategy.