July 2008
New Mixed-Language Flow and Platform Support for ispLeverCORE IP CoresDesign flow improvements ease adoption of IP core solutions.
Previously, Lattice has made its ispLeverCORE IP blocks available natively in Verilog HDL, supporting standard Verilog design flows. These blocks have been supported by design templates, simulation models and testbench models also coded in Verilog. This flow has been supported by the tools included in the standard ispLEVER design tool suite, making the process of evaluating and designing with Lattice IP very convenient for a wide range of users.
Lattice will continue to support its ispLeverCOREs in Verilog, however, we also aim to keep pace as designers’ needs for designing with IP change. These changes include the need to support mixed-language flows with VHDL design, as well as different computing platforms. To this end, Lattice has introduced new capabilities for users to easily evaluate and integrate ispLeverCORE IP blocks into their designs.
The addition of Aldec Active-HDL Lattice Edition to the ispLEVER 7.1 design software enables mixed-language simulation using the ispLeverCORE IP obfuscated Verilog model along with a VHDL model. Lattice’s ispLeverCORE design packages provide a simulation script just for this purpose, thus users can purchase ispLEVER from Lattice with no need to purchase additional third-party tools. Please see the iphelp file in each IP design package for more details.
ispLEVER 7.1 also includes Synplify Pro for mixed-language synthesis support. Synthesis is performed using the ispLeverCORE in Lattice .ngo format, Verilog modules, along with a VHDL template file for top-level instantiation of the ispLeverCORE IP block. As with Active-HDL, users need only purchase ispLEVER from Lattice to get access to this capability.
ispLEVER 7.1 Design Flow
A new change in ispLEVER 7.1 for Linux and UNIX users is the availability of Synplify Pro for both platforms, giving users the ability to perform mixed-language synthesis of ispLeverCOREs within the standard ispLEVER design flow. Mixed-language simulation for Linux and UNIX is also available by purchasing either Aldec’s Riviera verification tool or a full version of Mentor Graphics’ ModelSim for either platform.
Please note that for Linux/UNIX only, the ispLEVER Project Navigator cannot be used to perform either synthesis or simuation. However, Project Navigator can be used to perform place-and-route, as usual.
The following is a partial list of ispLeverCOREs which support mixed-language simulation and synthesis with the ispLEVER design flow. More IP cores are coming soon.
Users who have versions of ispLEVER prior to the 7.1 release (which includes Mentor Graphics’ ModelSim and Precision RTL Synthesis OEM Edition tools for Lattice), should contact their local Lattice sales office to learn how to migrate to the new mixed-language design flows.
Check out Lattice's ispLEVER 7.1 design tool suite to evaluate the new mixed-language design flows and platform support for ispLeverCOREs. Lattice’s goal is for 100% of its IP catalog to support mixed-language flow and Linux/UNIX platforms, so that designers can easily integrate IP into their designs and accelerate to production. Further information on ispLEVER can be found on the Lattice website.
© Lattice Semiconductor Corporation 2012
