January 2011Digital Visual Interface (DVI) is a video interface standard created by the Digital Display Working Group (DDWG) to replace the legacy analog VGA connector standard.
High-Definition Multimedia Interface (HDMI) is an industry-supported, all-digital audio/video interface for transmitting both uncompressed digital video and multi-channel audio over a single connector and cable that replaces various cables behind the home entertainment center.
DVI and HDMI have emerged as the dominant standards for connecting digital display devices such as PC monitors and HDTVs. DVI only carries uncompressed video data, whereas HDMI can transfer both uncompressed digital video and multi-channel audio over a single cable.
Both DVI and HDMI use Transition Minimized Differential Signaling (TMDS) technology for transmitting high-speed serial data. A TMDS link consists of a single clock channel and three data channels. This reference design takes advantage of the SERDES features in the LatticeECP3 FPGA devices to transmit and receive the TMDS signaling used by DVI and HDMI and achieving up to a full 1.65Gbps data rate in the low-cost FPGA.
LatticeECP3 HDMI/DVI Video Interface Reference Design was validated using the LatticeECP3 Video Protocol Board and HDMI Mezzanine Card. The reference design consists of the HDMI Transmitter and Receiver cores which are compatible with both HDMI and DVI physical layer protocols.
HDMI/DVI Receiver: HDMI and DVI serial data streams are recovered and de-serialized over three SERDES receive channels with a quad reference clock driven by the HDMI/DVI pixel clock. The embedded PCS Word Aligner detects the four Control Character patterns in the serial data stream and aligns the 10-bit TMDS character boundary before transmitting the data to the FPGA fabric for decoding.
HDMI/DVI Receiver and SERDES/PCS Block
HDMI/DVI Transmitter: The HDMI and DVI Transmitters encode the video pixel data, audio and auxiliary data (HDMI only), HSYNC/VSYNC and other control signals into three 10-bit TMDS data, and serialize them through the LatticeECP3 SERDES for high-speed transmission. An additional SERDES channel is used to transmit the pixel clock. Because the video and audio sources are all aligned before encoding, there is no need to implement channel-to-channel alignment and character synchronization for the HDMI/DVI Transmitter.
HDMI/DVI Transmitter and SERDES/PCS Block
In the loopback demonstration, the incoming HDMI signal is split into the video and data components and looped back through the output using the LatticeECP3 Video Protocol Board and HDMI Mezzanine Card. In addition, various manipulations are possible on both the data as well as the video.
LatticeECP3 HDMI/DVI Loopback Demo Block Diagram
© Lattice Semiconductor Corporation 2012
