January 2010A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8693. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
|---|---|---|---|---|
| Application Notes | ||||
| Powering Up and Programming the ProcessorPM ispPAC-POWR605 | Initial programming and power-up details are covered to assist engineers with trouble-free designs. Topics covered include the following: start-up state, behavior during JTAG programming, the "as-shipped" state of new devices, and reliable interfaces to power-supplies. |  |
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| Technical Notes | ||||
| LatticeECP3 Marvell 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability | This technical note describes a 1000BASE-X physical/MAC layer Gigabit Ethernet interoperability test between a LatticeECP3 device and the Marvell 88E1111 PHY. | |
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| LatticeECP3 Marvell SGMII Physical/MAC Layer Interoperability | This technical note describes an SGMII physical/MAC layer interoperability test between a LatticeECP3 device and the Marvell 88E1111 PHY. | |
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| Reference Designs | ||||
| GPIO Expander | The PLD-based general purpose I/O expander is ideal solution to provide additional I/Os to a microprocessor or microcontroller. | |
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| Simple Sigma-Delta ADC | This design targets the implementation of an analog- to-digital converter in a Lattice CPLD or FPGA. This reference design supports the use of an external analog comparator device, or optionally an on-chip LVDS buffer in devices with differential LVDS input support. Implementing this reference design can eliminate the need for dedicated and expensive analog-to-digital circuits (ADC), power supply monitors, and/or transducers. | |
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| Control Link Serial Interface | This reference design provides an example of how to implement a low-speed serial control link using Differential Manchester code. Now supports VHDL. | |
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| PCI/WISHBONE Bridge | This reference design provides an interface between the PCI initiator and the WISHBONE slave device. Now supports VHDL. | |
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© Lattice Semiconductor Corporation 2012
