January 2009

Lattice Listens

Q: What are the advantages of upgrading my ispLEVER software to version 7.2?  

A:  ispLEVER 7.2 is the latest FPGA design software from Lattice Semiconductor. ispLEVER 7.2 includes a number of performance and usability improvements. In addition, most of the major point tools have been enhanced to provide more of the features requested by users. The result is a more user friendly design tool that provides all of the tools necessary to quickly and easily complete a design implementation.

Performance Improvements

• Place and Route
  Using innovative new place and route techniques, ispLEVER can now analyze a design and automatically choose the most appropriate algorithm for the design’s topology. For example, in a design with a connectivity pattern that is more likely to lead to routing congestion, the software will automatically choose an algorithm that is appropriate to find better results in less time. In some cases, the chosen algorithm can reduce runtime as much as 30%.
• Auto-Hold Time Correction
  Auto-hold time correction is a process step that can be taken to find and fix hold time violations. Previously, this step could only be performed as an option in the place and route process. In some cases, it may be necessary to run auto-hold time correction several times to get the final results. For example, you may want to stop fixing hold violations from certain paths as they are “don’t cares”, and fixing them is leading to sub-optimal results. Prior to version 7.2, you would need to BLOCK these paths and re-run PAR again. In version 7.2, auto-hold time correction is also available as a separate process. Therefore, you can now BLOCK these paths and re-run only the auto-hold time correction process again, avoiding the time required for a PAR run.
• Clock Boosting
  Lattice “clock boosting” is now supported in the LatticeECP2/M FPGA families. Clock boosting is a method for increasing fmax by moving clock edges within a pipeline to effectively balance the pipeline. With very little effort, this methodology can increase fmax by up to 5%.

Usability Improvements

• Timing Analyze View
  The Timing Analyze view in the Design Planner allows you to quickly visualize your critical timing paths. It links from paths described in the Trace report directly to the design’s Floorplan view. In version 7.2, links for individual route segments and clock delay paths are now included, allowing you to visualize critical path components for both the data and clock paths and more quickly determine the cause of your timing issues.
• Clock Domain Analysis Report
  The Clock Domain Analysis Report has been added to the Trace Static Timing Analysis Report. This report is very useful in understanding the nature of the clock domains in a design, how they are constrained, and the datapaths that exist between them. By using this report as an example, you can quickly determine whether your clock domains are constrained (and how), whether the paths between your clock domains are constrained (and how) and whether there are datapaths between your clock domains that you may not have been aware of. This report helps you ensure that your timing constraints are complete and correct, and that you are closing timing on the right target.

Project Navigator

• User control of file scan and syntax check of the source file list

IPexpress

• Area optimization choice for Block Memory (EBR-based) generation
• Supports different read/write port widths on dual clock FIFO (FIFO_DC)

Design Planner Enhancements

• Interactive Trace Report (more active links)
• Improved REGION floorplanning with drag/drop assignment of logic groups to REGIONs

MAP / PAR Enhancements

• New MAP global control for I/O registering. Supports packing flip-flops adjacent to I/O ports to IOLOGIC registers of the sysIO Buffer.
• PAR automatic congestion driven options

Memory Re-initialization

• Memory initial values for distributed (i.e. LUT-based) memories can now be updated directly in a PAR’d design. The memory must support initial values feature. This extends existing support for block (i.e. EBR-based) memories.

Back-annotation

• Generation of compact netlist format is now extended to the LatticeXP2 FPGA family. This speeds up timing simulation sessions for large designs.

Timing Analysis (Trace)

• Improved accuracy for post-map static timing analysis (STA) reports. New algorithm uses route delay estimates to produce a result closer to post-route results. Gives faster access to a good estimate of the design’s final performance.
• Improved static timing analysis of generic DDR interfaces.
• New option for INPUT_SETUP and CLOCK_TO_OUT timing preferences allow you to analyze against a negative edge withoug updating the preference values whenever the clock frequency is changed. Available from the Design Planner.

Power Calculator

• Improved Power Calculator accuracy for I/O power consumption

Reveal Hardware Debugger

• New triggering function for contiguous events in trigger expression
• New triggering function for contiguous counts in trigger expression

ORCAstra

• ORCAstra on-chip configuration tool support now extended to the LatticeXP2 FPGA family