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The new Clock Domains Analysis section of the TRACE report is just one of the handy new features included with Lattice's recently-released ispLEVER 7.2 design software. The information contained in this report can be critical to verifying that your design is correctly constrained. Full story...
As engineers are pressured to cut costs and improve the reliability of circuit boards, an often overlooked opportunity is to reduce the number of components used for power monitoring. The ispPAC-POWR607 is an ideal solution that combines reset generation, watchdog timer (WDT) and voltage supervisor ICs into a single device. Full story...
Lattice's low-cost FPGA family is recognized in the Digital IC and Programmable Logic category. Full story...
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New Account
January 2009
