January 2008

Lattice Listens

Q: Which new features and enhancements are included in the new release of the LatticeECP2M PCI Express IP core?  

A: The new release of the LatticeECP2M PCI Express x1 and x4 version 3.1 is an ideal low-cost solution for PCI Express applications. This release includes the following enhancements to make the IP core easier to use as well as many new optional features:

• Message Signal Interrupt (MSI)
  The IP core supports the native PCI Express interrupt delivery mechanism (MSI) via pins created when the core is configured through IPexpress. The IP core automatically creates and sends Memory Write TLP for the corresponding MSI interrupt to the Root Complex when the user toggles the appropriate pin on the IP core. The IP core can be configured to support up to a maximum of eight MSI interrupts.
• PCI Compatible Interrupt (INTa)
  The IP core supports the optional legacy interrupt delivery mechanism (INTa) for the endpoint device via a pin. When the user design asserts/de-asserts the pin, the core automatically generates in-band messages targeting the interrupt controller in the Root Complex to assert and de-assert interrupt service requests. 
• Advanced Error Report (AER)
  The IP core supports the optional Advance Error Report mechanism. When this option is selected during configuration, AER registers are implemented inside the IP core to allow finer error definition granularity, uncorrectable error severity specification and report classification, error source identification, and error masking.  
• Error Message Generation
  The IP core automatically generates error messages such as Correctable, Non-Fatal, Fatal and Unsupported Request Error, depending on the settings of the related bits in the Device Control Register and taking into account whether AER is enabled. 
• IPexpress GUI Enhancements
  The IP core can now be configured entirely through the IPexpress GUI. New fields and tabs are logically arranged to guide users through the configuration process.
• Enhanced User's Guide
  The user's guide has been updated to make designing with the IP core even easier. Improvements include more complete pin descriptions, extensive interface timing diagrams, and a detailed description of the transmit/receive interface for requesting and completing packets.