January 2007

LatticeSC Performance Optimized After Rigorous Characterization

LatticeSC/M15 and LatticeSC/M25 go to full production.

After months of extensive qualification and verification, the first members of the revolutionary LatticeSC/M family, the LFSC/M15 and LFSC/M25 have been approved for full production.

Performance Improved in Several Key Areas

After full characterization, several performance enhancements are now fully verified:

• SERDES Transmit jitter is reduced to 0.25UI from 0.29UI at 3.2Gbps
• Receive Jitter Tolerance remains the industry's best at 0.8UI at 3.2Gbps
• SERDES maximum data rate is increased to 3.8Gbps. This is key for supporting proprietary, over-clocked XAUI schemes like HiGig+
• Added option for SERDES Transmit Amplitude Boost to increase eye height by 200 mV, p-p at the buffer
• MACO DDR2 performance increased to 667Mbps for flip-chip packages

New MACO Features Introduced on LatticeSCM80

The rollout of the LatticeSC/M family continues with larger arrays with even more differentiating features. Three new MACO (Masked Array for Cost Optimization) blocks are being introduced with the LatticeSCM80 device and will be supported in ispLEVER 6.1 SP2 (Feb 07):

• RLDRAM I/II MACO memory controller enables customers to interface directly to Reduced Latency DRAM memory which is commonly used as cache in embedded applications and as data buffering and table look up memory in telecom applications. This new memory controller operates at a maximum per pin rate of 800Mbps.
• Low Speed CDR MACO was developed for customers who want to support multi-rate serial protocols on a single pin where at least one of the rates is below the operating range of the SERDES. OC3/12/48 is the classic example of this. With the Low Speed CDR MACO, with a baud rate range of 100-500Mbps, all three rates can be supported on a single pin. Up to 18 data channels are supported in a single MACO block. The LS-CDR block can also operate in a synchronous mode, with the ability to receive 18 forward clocked parallel data bits using a single LS-CDR block.
• PCI Express LTSSM is now implemented in MACO rather than soft logic for all arrays with the exception of the LFSCM25. This reduces overall power consumption and the total gate count for the LatticeSC PCI Express solution is now a mere 5K LUTS for the entire protocol stack!

New AIL Reference Design Now Available

A new reference design that performs word alignment using LatticeSC/M's PURESPEED I/O INDEL (Input Delay) and AIL (Adaptive Input Logic) blocks is now available at no charge. This design simplifies the task of word deskew for dynamically aligned parallel I/O busses using an innovative data bus deskew scheme developed by Lattice engineers in conjunction with the pre-engineered INDEL and AIL blocks For more information or to arrange a demonstration, please contact your local Lattice Sales Representative.