January 2007

Contents

Single-Chip Solutions Simplify PCI Express Design

Lattice is the only FPGA company to offer both low-cost and high-performance single-chip solutions for PCI Express.

Lattice's PCI-SIG Certified PCI Express solutions provide designers with intelligent choices for implementing PCI Express systems to meet a wide variety of system and cost requirements. Until now, designers considering FPGAs for PCI Express could only choose from low-end FPGAs requiring additional external PHY chips or very expensive high-end FPGAs with embedded SERDES channels. With built-in embedded SERDES channels and PCI Express clock management support, LatticeECP2M and LatticeSCM PCI Express solutions illustrate Lattice's corporate philosophy of "More of the Best", combining the best 90nm FPGA silicon technology with the best FPGA architecture and features to deliver more performance cost-effectively for a range of systems.

Lattice PCI Express Solutions
	Shared Features	LatticeECP2M Specific Features	LatticeSCM Specific Features
Feature Set	Embedded SERDES channels that support operation at full PCI Express 2.5 Gbps line rate PCI Express 100 MHz reference clock Compliant with PCI Express jitter specifications	Low-cost FPGA fabric Small footprint packages Cost-optimized SERDES channels	High performance FPGA fabric Multi-protocol SERDES 2Gbps parallel I/O Pre-engineered hard IP core
Endpoint IP Solution	Standard feature in Lattice's ispLEVER design tool suite IPexpress: download, install and configure No charge!	x1 Transaction, data link, and most of the physical layer (PHY) implemented in a soft IP core Remaining PHY implemented in SERDES/Physical Coding Sublayer (PCS) 5600 LUTs	x1 and x4 Transaction layer in soft IP Data link and PHY layers implemented in pre-engineered flexiPCS, LTSSM and flexiMAC MACO hard IP blocks 5500 LUTs (x4 solution)
Typical Applications		High-volume, form-factor sensitive applications such as add-in cards and mini-cards	System integration or complex functions such as bridging or switching

Lattice PCI Express IP Core Protocol Support

When combined with Lattice's PCI Express evaluation boards, free demos, and drivers, creating and evaluating a PCI Express design with Lattice becomes a quick and low-risk proposition. Lattice offers the LatticeECP2M PCI Express x4 Evaluation Board. Lattice also offers two LatticeSCM boards - the LatticeSCM25 and LatticeSCM80 PCI Express evaluation boards with x1 and x8 link width connectors respectively.

PCI Express Evaluation Board and Demo/Driver Setup

PCI Express and Compliance/Interoperability

PCI-SIG (PCI Special Interest Group) is the international standard body responsible for developing and maintaining PCI Express specifications. PCI Express is a state-of-the-art packet-based serial interconnect technology and architecture that retains the PCI software usage model and software interfaces to protect infrastructure investment and ensure smooth migration. The technology is aimed at multiple market segments and supports chip-to-chip, board-to-board, and adapter solutions at an equivalent or lower cost than current PCI designs. PCI Express currently runs at 2.5 Gbps per lane in up to a current maximum of 32 lanes.

The LatticeECP2M and LatticeSCM cores and evaluation boards are compliant with version 1.0a of the PCI-SIG PCI Express specifications, ensuring designers that Lattice's solutions are reliable, have been rigorously tested against the highest standards, and are interoperable with other PCI Express hardware. This makes Lattice a safe and dependable choice for implementing PCI Express designs.

PCI Express Interface

PCI Express Applications

PCI Express is the next-generation successor to the ubiquitous PCI and is popular in a number of embedded, computing, and communications applications. Typical applications include root complex, bridge, switch, and endpoint applications as illustrated below.

PCI Express System Topology