January 2007
Lattice is the only FPGA company to offer a mixed-language simulator based on Aldecs Active-HDL Designer Edition tools.
As the scale and complexity of FPGA designs increase, designers often leverage intellectual property from a variety of sources and formats. The Aldec-HDL Lattice Designer Edition Lite simulator includes key simulation features required by FPGA designers to help debug and verify designs that incorporate both Verilog HDL and VHDL source. The simulator provides a common kernel simulator engine to mix VHDL and Verilog, trace code execution, and scripting via Tcl/Tk and Perl. The GUI supports display of waveforms, lists, and sub-program calls. All configurations of Active-HDL have been qualified with Lattice model resources and support all Lattice FPGA devices including the LatticeECP2/M, LatticeSC/M, and LatticeXP.
Aldec, an EDA tool provider established in 1984, offers a suite of of high-performance design verification tools for FPGA and ASIC devices. Active-HDL, Lattice Designer Edition Lite is available for Microsoft Windows XP/2000/NT.
An annual license is $1249 from the Lattice Online Store. An evaluation is available for download on the Design Software page of the Lattice website.
Aldec-HDL Lattice Designer Edition Lite Graphical User Interface
© Lattice Semiconductor Corporation 2012
