January 2007
Embedded microprocessor trends and challenges.
Use of embedded microprocessors in FPGA designs is here to stay. Technological advances are removing roadblocks to soft processors, allowing designers to exploit their inherent benefits. The LatticeMico32 soft processor provides a complete embedded design platform that is easy to use and pioneering in its open source license. Lattice's unique open IP core licensing agreement, along with software development tools under their respective open source licenses, such as Eclipse and GNU, provides designers with visibility, flexibility, and architecture portability. Adding its WISHBONE bus interface and port of Micrium's μC/OS-II RTOS, the LatticeMico32 soft processor is a complete embedded microprocessor design solution.
The last few years have witnessed a growing trend in the use of embedded microprocessors in FPGA designs.
FPGA Design Starts with Embedded Microprocessors (Source: Gartner, August 9, 2005)
This trend of the embedded microprocessor approach is being driven by four important benefits:
Along with the benefits highlighted above, another reason more designers are using an embedded option is that their historical challenges are being removed:
Cost: Historically, off-the-shelf microprocessors have been significantly less expensive than their embedded counterparts. Today, with the latest low-cost FPGAs, the costs are equivalent. For cost sensitive applications, such as consumer products, using an embedded microcontroller is now a viable approach. Low-cost FPGAs are proving to be a cost-effective solution because they consume minimal resources and, if a design already uses an FPGA, the processor can be integrated into the FPGA, saving the cost of a discrete part or a new FPGA.
Time to Market: Designers of system-level chips that include embedded microprocessors have two key time-to-market concerns. First, how quickly can the hardware associated with the microprocessor sub-system be architected and implemented? Second, how long will it take to write, test and debug the code that runs on their microprocessor? Over the last few years, development software for embedded microprocessors has improved greatly in its overall usability and ease of use. As a result, a design can be up and running in a matter of minutes. Design tools also allow for software and hardware debug, change and upgrade activity, which make an embedded microprocessor even more appealing. Time to market is reduced because it is much quicker and simpler to implement functionality in software than it is to design it in hardware.
Performance: Performance has been historically better with off-the-shelf microprocessors. With improved technology, however, FPGAs have advanced significantly in their feature sets and in overall system speeds. With FPGAs now able to handle greater bandwidth, embedded processors have become attractive choices for many designs.
The LatticeMico32 is a RISC architecture microprocessor based on Harvard style addressing. The RISC architecture provides a simpler instruction set and faster performance. The Harvard style addressing allows for single cycle instruction execution, because the instruction and data buses are separate, allowing for simultaneous access. The data and instruction paths are both 32-bit and 32 general-purpose registers are provided. The LatticeMico32 can handle up to 32 external interrupts. Optional Instruction and Data caches are available. The figure below highlights these features, as well as other components.
LatticeMico32 Block Diagram
To accelerate the development of processor systems, several optional peripheral components are available with the LatticeMico32 microprocessor. These components are connected to the processor via a WISHBONE bus interface, which is a royalty-free, public domain specification maintained by OpenCores.org. By using this open source bus interface, users have the ability to incorporate their own WISHBONE components into their embedded designs. The peripheral components include:
The LatticeMico32 System software development tools provides a fast and easy way to implement microprocessor designs from platform definition to software development and debug. The tools are based on the Eclipse C/C++ Development Tools (CDT) environment, which is an industry standard open-source development and application framework for building software (see screen shots below).
The LatticeMico32 System is comprised of three integrated tools: the MicoSystem Builder (MSB), the C/C++ Software Project Environment (SPE), and the Debugger. The MSB generates platform descriptions and the associated Hardware Description Language (HDL) code for hardware implementation. Designers can choose which peripheral components to attach to the microprocessor, as well as specify the connectivity between them.
MicoSystem Builder (MSB)
The C/C++ SPE calls a compiler, assembler and linker and enables the development of code targeted to run on platforms created with the MSB. It is through the C/C++ SPE that platforms created in MSB can be referenced.
C/C++ Software Project Environment (SPE)
Finally, the Debugger, which is a C/C++ source debugger, provides the ability to debug in assembly and watch the processor registers and memory. Designers can observe and control the execution of the code in both an Instruction Set Simulator (ISS) and in physical hardware.
C/C++ Source Debugger
Real-Time Operating System (RTOS): Additionally, to further facilitate microprocessor designs, included with the LatticeMico32 System is a port of Micrium's μC/OS-II RTOS. The use of an RTOS helps divide complex software into simpler and more manageable threads of execution by alleviating task scheduling and synchronization and handling multiple tasks. With an RTOS, designers can easily scale, manage, and maintain their software, which results in a quicker time-to-market. The port of Micrium's μC/OS-II RTOS is included in the software for evaluation and non-commercial purposes. For commercial purposes, a license needs to be obtained directly from Micrium. Some of the key features of Micrium's μC/OS-II RTOS include:
Open source is gaining popularity in a variety of software areas and is already well established for desktop/server software. What about Intellectual Property (IP) in the Field Programmable Gate Array (FPGA) arena? Is this the next trend? Are we at the early stages of a new phenomenon?
Before we answer these questions, it's necessary to examine the benefits of using open source IP, which include more visibility, greater flexibility and improved portability. Open source provides visibility into the details of the microprocessor. By having access to the source code, a designer has a complete understanding of the details of the core.
Additionally, open source provides greater flexibility in that the IP is available and open for everyone, so designers can review it and make improvements to the IP. The entire user community helps to identify problem areas and to develop solutions. This means that not only are modifications permitted, they are encouraged. This community interaction results in an open source IP core that tends to be more robust and reliable than traditional, proprietary IP.
Finally, open source provides improved portability. A user enjoys architecture independence because an open source IP core can be used in any FPGA, or even migrated to an ASIC for higher volume, mature designs. Architecture independence is valuable because it provides insurance in case last minute changes need to be made in the silicon. In addition to these, the most commonly associated benefit of open source IP is that it is free of charge.
Standard Open Source Licensing Restrictions: Today, many open source licenses exist. Three of the most common ones are:
Although open source licensing is available, the hardware design community has not rushed to use open source IP. As powerful as the benefits are, the reality is that standard open source IP licensing, such as the ones mentioned above, does have some restrictions that can be major stumbling blocks.
For example, some of these licenses impose certain responsibilities for the distribution of derived works. In this case, FPGAs that utilize the source code are considered derived works. The entire derived work must therefore be made available in source form. As a result, any proprietary logic becomes public, which is clearly not desirable.
Another issue is that open source licenses typically require the user to provide a copy of the license with the derived work. In many cases, having to send out a license with each end product can be at best inconvenient and at worst impractical. In effect, standard open source licensing has restrictions that may limit, or forfeit, the user's ability to maintain designs as proprietary.
Lattice Eliminates Open Source Licensing Restrictions: For users who may be apprehensive about standard open source cores, Lattice provides a unique open IP core licensing agreement. The agreement provides all the benefits of standard open source, while also addressing the drawbacks of standard open source licensing by breaking down the core into modules. Each module must be available free of charge, but the rest of a user's design can be licensed under any user chosen license agreement. Furthermore, the agreement allows programmable logic devices to be distributed containing the design without the need to distribute the license agreement or source. In short, the Lattice open IP core licensing agreement allows users to mix proprietary designs with the open source core and distribute the designs in bitstream or FPGA format without an accompanying copy of the license.
For the LatticeMico32, the licensing structure is two-fold. The Lattice open IP core license agreement will be used with the HDL code that is generated by the MSB tool. Most of the graphical user interfaces will be licensed under an Eclipse license, while, for the internal workings of the software, such as the compiler, assembler, linker, and debugger, the licensing scheme will follow the GNU-GPL.
The LatticeMico32 is a complete embedded microprocessor design solution. When used with Lattice's FPGAs, designers have a cost effective design alternative. The LatticeMico32 development tools make it easy to implement a microprocessor and the attached peripheral components in an FPGA. The ease of use ensures that design times are minimal, which result in an even quicker time to market. Through various flexible configurations, the LatticeMico32 can be tailored for customers with performance requirements. Lattice is a pioneer in the open source microprocessors arena. By providing the generated HDL under an open source license agreement and the software development tools under their respective open source licenses, such as Eclipse and GNU, Lattice allows users complete control of their designs. The open source nature provides designers with visibility, flexibility, and architecture portability.
© Lattice Semiconductor Corporation 2012
