January 2007

Lattice Listens

Questions:

1. Can I use the LatticeECP2/M for LVDS source synchronous interface?
2. What is the best way to get my technical support questions answered?
3. Has Lattice performed interoperability experiments with 3rd party devices?
4. Why should I use a Power Manager as a hot-swap controller in a PCI Express adapter card?
5. Why should I use a POWR-6AT6 to set the power supply voltage of a DC-DC converter?

Can I use the LatticeECP2/M for LVDS source synchronous interface?

The LatticeECP2/M is an ideal low-cost solution for the LVDS source synchronous interface. Lattice demonstrated the LVDS source synchronous interface with the 7:1 LVDS Video interface reference design. The 7:1 LVDS Video interface (Camera Link) design utilizes the pre-engineered DDR I/O registers of the LatticeECP2 and LatticeECP2M device families to achieve up to 600 Mbps of LVDS bandwidth per serial channel. Any generic LVDS source synchronous interface can be implemented in the same manner in the low-cost FPGA with no additional IP to achieve this bandwidth.

What is the best way to get my technical support questions answered?

Lattice provides an extensive technical support network designed to assist customers of all levels of expertise in finding answers to their technical questions and support issues.

For hardware related questions Lattice provides numerous documents covering all aspects of our devices. Lattice has generated device specific handbooks for our FPGA devices that put the most requested documents together in a single document for each specific device family. Each handbook includes a device data sheet, which gives an overview of the device family and features, DC and switching characteristics, pinouts, and ordering information. The handbook also includes a list of technical notes that describe in detail specific hardware features, how to use software point tools with the device, and HDL coding style guides to help achieve the best performance for the device family. These as well as a multitude of other device-specific and device-independent documents can be found on the Lattice website at www.latticesemi.com

For software related questions, Lattice has recently enhanced our ispLEVER online help system by organizing subjects by device category, providing more targeted information, faster searches, and an improved index and glossary. The ispLEVER online help has been integrated into the Lattice website, providing a seamless link between the software and pertinent documentation, such as data sheets, technical notes, and application notes. This integrated help is a powerful tool to quickly access the entire library of information available from Lattice.

Lattice’s online user forums, provide a means to access an extensive array of information in numerous hardware and software specific forums. The forums include internally generated frequently asked questions (FAQs), and the ability for users to ask questions and exchange design ideas between themselves, other users and Lattice.

Finally, users can always contact the Lattice Technical Support group directly with questions. The technical support group is available Monday through Friday 8:00 am to 5:00 pm PST. Users can reach the technical support group by phone using the following numbers:
For USA & Canada: 1-800-LATTICE (528-8423)
For other locations: 503-268-8001

Or send email to: techsupport@latticesemi.com

Has Lattice performed interoperability experiments with 3rd party devices?

Lattice has performed several interoperability experiments with 3rd party devices. Interoperability experiments have focused on Gigabit Ethernet interfaces, 10-Gigabit Ethernet interfaces and 10-Gigabit Packet interfaces. The following specific interoperability tests were performed.

• Gigabit Ethernet Interface using the LatticeSC’s flexiPCS (Physical Coding Sublayer) configured in the Gigabit Ethernet mode can be connected directly to the Marvell Alaska family of products through a Gigabit Ethernet SERDES. See TN1120 for more information.
• Serial Gigabit Media Independent Interface (SGMII) using both LatticeSC’s flexiPCS and LatticeECP2M’s PCS block coupled with Lattice’s own SGMII IP can be connected directly to the Marvell Alaska family of products. See TN1127 for more information.
• 10-Gigabit Attachment Unit Interface (XAUI) using LatticeSC’s flexiPCS configured in the 10-Gigabit Ethernet mode can be connected directly to the Marvell Alaska X transceivers through the XAUI interface. See TN1128 for more information.
• 10-Gigabit Packet Interface (SPI4.2) interoperability test with the LatticeSC device family and PMC-Sierra S/UNI family was performed. The LatticeSC family has one or two fully characterized hardwired SPI4.2 interfaces. Each is fully compliant with OIF-SPI4-02.0 specification, offering up to 256 logical ports, with transmit/receive data paths that are 16 bits wide with in-band port address, SOP, EOP indication, and error control. The goal of the test was to prove the interoperability between LatticeSC SPI4.2 interface and PMC-Sierra’s PM3388 POS-PHY Level 4 system interface. See TN1121 for more information.

All interoperability reports can be found in the respective device application notes section of the Lattice website.

Why should I use a Power Manager as a hot-swap controller in a PCI Express adapter card?

The in-rush current of a PCI Express card during start-up can exceed the current limits specified by the standard because it depends not only on the bulk capacitor connected to the power supply but also on the turn-on characteristics of the ASICs/FPGAs/CPUs used on the board.

The in-rush control circuit using the Power Manager device, ispPAC-POWR1014, limits the in-rush current to the specified limits across all load conditions. Additionally, the current limit also can be programmed to suit different PCI Express configurations in-system.

A single-chip POWR1014 device, in addition to limiting the current in-rush, also integrates voltage supervisors, CPU-reset generators, power supply sequencing ICs as well as watchdog timer ICs. Consequently, a POWR1014 device can be used as a standard power management solution across all the PCI Express adapter card designs.

The POWR1014 also stretches the input PERST# signal to meet different start up delays, thus providing designers with the flexibility to use larger FPGAs on their boards.

Why should I use a POWR6AT6 to set the power supply voltage of a DC-DC converter?

Typically the output voltages of DC-DC converters are set using external resistors. While this is a simple solution, it has a few limitations: Implementing power supply margining requires switching between resistors in the feedback path and the output voltage accuracy of the DC-DC converter depends on its internal VREF accuracy and the resistor accuracy. The output voltage error reduces the headroom available for the transient response.

The POWR6AT6 not only improves the accuracy of any DC-DC converter to less than 1% but also enables the implementation power supply voltage margining through digital control or through an I²C bus, thus converting a low cost DC-DC converter in to an accurate, digitally controlled power supply.