January 2007
New ispPAC-POWR607 device ideally suited for handheld systems requiring very low standby power.
Recently, Lattice announced the addition of the programmable, ultra low cost ispPAC-POWR607 device to its second generation Power Manager II product family. The new devices achieve a sub-$1.00 price point in high volume, targeting many cost-sensitive power management applications in consumer markets such as LCD TV, automotive multimedia systems, GPS receivers, multimedia terminal adapters and set-top boxes. The ispPAC-POWR607 device integrates a complete set of power management functions that typically require multiple ICs.
The POWR607 device provides ideal support for any 16-bit or 32-bit microprocessor-based system. Designers have traditionally used a design-specific set of discrete off-the-shelf devices to generate the CPU Reset, Power Supply Fault Interrupts and Watchdog Timers for each microprocessor-based design. The POWR607 device can implement all these functions through logic programmed into its on-chip CPLD, which results in a standardized, lower cost design solution.
The Power Manager II devices are programmable logic devices plus analog peripheral circuitry optimized for power management functions. Because these devices are software programmable, each of the five family devices can replace any combination of supervisory devices, reset generator devices, hot-swap controllers, power supply sequencers and power supply trimming and margining circuits, as well as multiple resistors and capacitors. Consequently, a Power Manager II device reduces both the bill-of-material cost and the time to market.
The POWR607 device uses Lattice's award-winning Power Manager architecture. The device can monitor up to 6 circuit board power supplies and generate signals such as a CPU Reset, including pulse stretching and power supply fault interrupt, using the on-chip 16 macrocell CPLD, four programmable timers and 7 outputs (two of which also can be configured as high voltage MOSFET drivers). The POWR607 device can be powered down using an external logic signal, or by an internally generated signal. Once in the power down state, the device draws a mere 10 microamperes from the power supply. The POWR607 devices are packaged in the space-saving 5mm x 5mm QFN package.
ispPAC-POWR607 Block Diagram
Due to its low cost, very small footprint and low power standby feature, the ispPAC-POWR607 is an ideal power management solution in handheld consumer, telecom and industrial applications.
ispPAC-POWR607, the Ideal Support Chip for Any Microprocessor
All Power Manager devices, including the POWR1220AT8, POWR1014/A, POWR6AT6 and POWR607, provide a standard, off-the-shelf programmable mixed-signal solution for power management across multiple circuit boards. This solution improves reliability, speeds time-to-market and reduces cost.
Designs for the ispPAC-POWR607 are implemented using the Windows-based Lattice PAC-Designer software version 4.7 and above. PAC-Designer 4.9 software is available for download free of charge from the Lattice website.
© Lattice Semiconductor Corporation 2012
